Rambus INC jobs

PE Signal Integrity Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PE Signal Integrity to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities . Qualifications Solid background in SI/PI. B.E/Btech/MS/Mtech in Electronics/Electrical Engineering with 8+ years of industry experience. Strong theoretical background and understanding in EM and transmission line theory is a must. Solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required. Good understanding of crosstalk, Jitter and PDN concepts. Must understand package and PCB design. Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required. Exposure to commercial EDA tools such as ADS, HFSS, Q3D, Siwave, Hspice etc. Familiarity with Totem is a strong plus. Some exposure to ATE is desired, but not mandatory. Good to have experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc. Decent writing and presentation skills are essential as well as good communication skills to work with cross-functional teams. Must be an innovative, self-motivated and a team player. About Rambus Rambus is a global company that makes industry-leading memory interface chips

Hardware Design Engineer Hillsboro, OR, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Design architecting and trade-off analysis RTL coding and verification Memory Controller + PHY integration and verification Customer delivery and support Qualifications Strong System Verilog/Verilog RTL design expertise Questa/Incisive/VCS simulator experience Python/Perl/Tcl scripting experience Significant ASIC and/or FPGA design experience Ability to learn quickly and work independently Solid communication and project management skills 5+ years of logic design experience BSEE Definite Plus: ASIC synthesis, timing constraint, CDC/RDC experience Verification experience Memory (HBM, GDDR, LPDDR, DDR) expertise AMBA AXI or CHI design experience Located in the Hillsboro, Oregon area Training: Provided as needed About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our

Principal Test Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Principal Test Engineer to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Define the Test plan and work with design to ensure good Test coverage. Effective communications skills with internal cross functional teams, customers and suppliers. Able to design ATE hardware for NPI support, including Load Board, probe card, interface Complete life cycle of products from design, prototypes, high volume manufacturing bring up and RMA/sustaining support. Optimize yield, Test time and multi-site count. Qualifications B.S./M.S. in Electrical Engineering or equivalent experience. Experience with Test coverage and DFT (Scan/ATPG/JTAG/BIST). Experience working with Local and offshore OSAT's. Experience and in-depth knowledge of Advantest V93k. Experience on Smartest, Redhat and GIT/SVN. Experience in DDR and High-speed Digital products preferred. Ability to independently learn and problem solve. Comfort with collaboration, open communication and reaching across functional borders. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and

PE Physical Design Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Own end-to-end physical implementation for major IP blocks and/or full-chip designs. Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus). Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability. Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements. Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones. Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability. Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement. Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results Qualifications Must have minimum Bachelors degree in EE/ECE (degree's related to electronics) from a reputed institute. Must have at least 10 years of experience, out of

CAD Infrastructure Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional CAD Infrastructure Engineer to join our Central CAD Team. Selected candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a CAD Infrastructure Engineer, the candidate will be reporting to the Director of CAD. In this role the candidate will be working on CAD tool, flow and methodology development and support for a world-wide design team working on advanced process technology nodes. The CAD team is spread globally across the US and India and supports EDA (electronic design automation) software, EDA infrastructure, design flows/methodologies, and design automation for world-wide design teams working on cutting edge product chips designs for memory interface chips, interconnect chips and silicon IP designs. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Work as part of a computer-aided design (CAD) team that architects, develops, and delivers software tools and workflows that are critical to Rambus's advanced chip design and verification. Own the development, support, and continuous improvement of CAD infrastructure in a global environment with multiple chip design teams and heavily shared computing resources. Design, configure, and optimize LSF queues and policies to maximize chip design job

Digital IC Design Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional MTS Digital Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Work with analog/digital design team for new product development Responsible for RTL coding, functional simulation, analog-block Verilog model, post-pr simulation Support bench test, support ATE test Support chip bringing-up, debugging, failure analysis, characterizations and product release efforts Qualifications Master degree or above in EE or related field At least 3 years of digital IC design experience Experience in the area listed below: Embedded SRAM/OTP/Efuse/MTP controller Design for test for digital block, analog block Communication bus such as I2C/I3C/SPI/AHB/APB Familiar to schematic editor Being Familiar to mixed signal design and backend is a plus Mass product experience is a plus Self-motivated and proactive Good communication skills and a strong team player About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience,

VP Global Operations San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional VP of Operations to join our Operations Business Unit in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. In this role, you'll be accountable for end-to-end operational execution, ensuring on-time delivery, cost competitiveness, supply continuity, and continuous productivity improvement. The VP of Operations will build and run a resilient global operations organization spanning foundry and OSAT management, materials strategy, planning, logistics, NPI/production ramp, and operational risk management-while partnering closely with Engineering, Marketing, Sales, Finance, and key external manufacturing partners. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Establish operational governance for allocation, prioritization, and revenue attainment during constraints. Establish supply risk assessment and mitigation plans: geopolitical risk, node constraints, single-source dependencies, logistics disruptions, and disaster recovery. Build business continuity playbooks: alternate sites, qualified alternates, safety stock strategy, and rapid reallocation processes. Work in a fast-paced, exciting environment with strong business acumen to drive value to business Works collaboratively and cross functionally to meet the businesses needs and optimize revenue and margin Identifies risks and problems in timely manner and drives resolution with speed

MTS Analog Engineering Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional MTS Engineer Analog Design to join our memory interface chip design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a MTS Analog Engineer - Analog Design, the candidate will be reporting to Sr Manager Engineering and is a Full-Time position. The candidate will be leading the analog mixed signal circuit design activities for high-performance mixed signal chip products. Rambus memory interface chips team delivers the most advanced chipset solutions for server memory sub-system. This role gives opportunities to invent solutions to improve performance of next generation high-performance mixed signal products and learnings opportunities working through all the phases of chip product design all the way from concept to volume production. Responsibilities Ownership of Analog/Mixed designs at chip and/or block level. Define optimal architectures to achieve competitive product specifications. Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, LDO, PLL, DLL, PI circuits). Create high level models for design tradeoff analysis and behavior model for verification simulations. Create floorplan and work with layout team to demonstrate post extraction performance. Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow. Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion. Participate and drive post silicon validation, debug,

SMTS Verification Engineering Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SMTS Verification Engineer to join our Memory Interface chips team in Bangalore . In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a SMTS Engineer, you'll play a pivotal role in (DDR Verification, starting from understanding the design till Verification sign-off, and also to support the Validation team post-tapeouts ). In this full time role, you'll report directly to our Director. Our MIC team is dedicated to produce high speed DDR products at a high quality to meet the industry requirements, and your contributions will be instrumental in closing the Verification requirements of these products. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work Responsibilities Understand the product requirements from the specifications and beyond Planning and execution to meet the verification sign-off criteria Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system using UVM methodology Guide and mentor the team to meet the sign-off requirements Work with architects, designers and post-silicon teams Qualifications Bachelor's or Master's degree in Electronics with 5+ years of relevant experience Expertise in System verilog and UVM Strong debugging

Sr Principal Test Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Sr Principal Test Engineer to join our Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Define the Test plan and work with design to ensure good Test coverage. Effective communications skills with internal cross functional teams, customers and suppliers. Able to design ATE hardware for NPI support, including Load Board, probe card, interface Complete life cycle of products from design, prototypes, high volume manufacturing bring up and RMA/sustaining support. Optimize yield, Test time and multi-site count. Qualifications B.S./M.S. in Electrical Engineering or equivalent experience. Experience with Test coverage and DFT (Scan/ATPG/JTAG/BIST). Experience working with Local and offshore OSAT's. Experience and in-depth knowledge of Advantest V93k. Experience on Smartest, Redhat and GIT/SVN. Experience in DDR and High-speed Digital products preferred. Ability to independently learn and problem solve. Comfort with collaboration, open communication and reaching across functional borders. About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between

Lead Sourcing Analyst San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Sourcing Analyst to join our Memory Interface Chip team in San Jose, CA or Taiwan. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Lead Sourcing Analyst, the candidate will be reporting to the Director Sourcing and is a Full Time position. This role is responsible for defining and implementing all aspects of current and long-term sourcing strategies to effectively source foundry and OSAT that meet customer expectations of supply, quality, technology, and cost. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Responsibilities:· Supplier management; own commercial interface & supplier negotiations with key suppliers· Monitor supplier performance & KPI's including supply, cost, quality, and technology· Project management; drive projects as both project leader and/or member supporting strategic initiatives· Develop and maintain cost projection and perform data analysis that can be leveraged in negotiation and sourcing strategy· Lead mid-long term planning activities and actively seek opportunities for process improvements· Drive and sustain effective communication with internal and external partners Qualifications Qualifications:· 10+ years of experience to manage semiconductor related materials, suppliers, and have interactions with ASIC houses, fabless, OEM,

Sr. Principal Verification Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SPE Verification Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Understand the architecture of the chip and functional blocks. Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures. Create testplan and develop test cases/sequences in UVM. Debug functional issues in the DUT based on the good understanding of the architectural specification. Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project. Qualifications MSEE/BSEE, CS or related field 7-10+ years experience Proficient in Verilog, systemverilog and UVM. Familiar with Linux environment and the industry's prevailing EDA tools. Have better understanding of Verification methodology and concepts. Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release. Have excellent communication skills (both written and oral) and cross-team/function collaboration capability. Experienced in code coverage and functional coverage closure. Strong problem-solving skills. About Rambus Rambus is a global company that makes

Principal Field Applications Engineer San Jose, UNAVAILABLE, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Field Application Engineer to join our Sales team. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Contribute to Rambus revenue growth through direct and indirect technical activities. Develop a solid technical understanding of our products and relevant solutions. Provide deep technical support to customers to meet or improve upon customer's requirements with Rambus products, specifically RCD, CKD, PMIC, SPD and TS. Provide thorough customer design support including schematic and PCB layout review Identify and develop new business opportunities to grow Rambus business. Gather potential market moves and competitors' activities for Rambus product strategy. Qualifications Bachelor in Electronics or Electrical Engineering with 5+ years of Registering Clock Driver (RCD) or power management IC (PMIC) experience. Experience with JEDEC memory standard, Intel and/or AMD memory subsystem requirements and specifications preferred. Ability to interface directly with customers and solve customer problems. Ability to work independently with strong analytical skills, self-motivated and excellent interpersonal skills. Ability to communicate at all levels written and oral. About Rambus Rambus is a global

Technical Director Validation Johns Creek, GA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Technical Director Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The Technical Director Validation Engineer is a Full-Time position and the candidate will work in the lab to automate data collection and provide framework to develop validation environment to check system performance and specification compliance. The candidate is required to have experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Lab bring-up and validation of high-speed memory buffer semiconductor products. Develop test methodologies for validating silicon designs against specifications. Develop scripts for automating lab equipment and for analyzing lab data. Lead validation tasks on bench planning, preparation, characterization execution, methodology improvements. Work with silicon design teams to develop experiments, drive data collection, and present results analysis. Provide inputs to FPGA, system, and PCB design requirements. Support Applications Team in understanding and resolving customer issues. Qualifications Experience in Bench testing and characterization of high speed and/or memory IO devices, exposure to DDRx characterization is preferable.

Senior Package Design Engineer San Jose, CA, US; Taipei, UNAVAILABLE, TW Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Package Design Engineer to join our Package Engineering team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. This is a full-time position reporting to the Director of Package Engineering. As a Senior Package Design Engineer, you will be responsible for supporting the design and layout of new products from early concept to tape out, focusing primarily on several elements that enable high-yielding, low defectivity production. The Senior Package Design Engineer will have the opportunity to work with multiple package technologies and outsourced suppliers to ensure manufacturing readiness for the Rambus product portfolio. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Drive early chip-package co-design and development of bump and ball map. Own layout of package types such as FCCSP, FCBGA, FCQFN, WLCSP, QFN. Collaborate with multiple cross-functional teams (Chip Design, SI/PI, Packaging) Analyze cost/performance/reliability trade-offs to complete layout of new products and test chips. Interact with OSAT partners and substrate/leadframe suppliers for design reviews and execution. Continuous improvement of package design workflow and unified package design guidelines.

Sr Mgr Product Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Sr. Manager Product Engineering to join our Global Operations team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Sr. Manager Product Engineer, you'll play a pivotal role in (add brief overview of key responsibilities and impact). In this full time role, you'll report directly to our VP of Global Operations. Our Product Engineering is dedicated to rolling out new products to our OSAT's, and your contributions will be instrumental in the Cost of test and Quality. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Hiring manager lists a thorough and current list of the major duties and responsibilities of the position. Organize it from most to least important. Manage a team of Product Engineers located in multiple countries. Project management with effective communications skills with internal cross functional teams, customers and suppliers. Communicate weekly product status and updates on yield, OEE and quality trends. Execute effective teamwork by collaborating with global teams to enable new product introductions at the OSAT's. Enable product Test Flow implementation to ensure lowest Cost of

Sr Principal Signal Integrity Engineer Shanghai, UNAVAILABLE, CN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SPE Signal Integrity Engineer to join our Memory Interface Chip business unit in Shanghai, China . Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a SPE Signal Intergity Engineer, the candidate will be reporting to the VP Engineering and is a Full position. The candidate will work within our SI/PI team on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speeds up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed Qualifications Solid background in SI/PI and package design to provide technical leadership to the team Strong interpersonal skill to keep the team motivated and focused MS or PhD

Lead MTS Analog Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead MTS Analog Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Primary focus will be the products IO ESD/LU/EOS area, design & maintain the centralized ESD/LU/EOS design across multiple products. Create Chip/block level floorplan and work with mask designer to complete layout. Work with package engineering to create bonding diagram. Ownership of Analog/Mixed signal designs at chip and/or block level Chip level integration Work closely with Digital team to define analog/digital interface. Design, simulate and characterize analog/mixed signal circuits (e.g. Bandgap, Bias, LDO, IO, DC-DC BUCK, etc). Create and maintain test documents for test and validation engineering Work with the Lab/Validation team for test plan, silicon bring up and characterization Work closely with cross functional teams from different geographies and time zones to ensure engagement and execution Other responsibilities include design documentation and post silicon activity support Qualifications Deep understanding the process device ESD/LU/EOS. Deep understanding ERC/DRC/LVS. Competent in using fast simulator (CustomSim, XPS, AMS) for

SMTS Foundry Technology Taipei, UNAVAILABLE, JP Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SMTS Foundry Technology to join our Operations Engineering team in Taiwan. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a SMTS Foundry Technology, you'll play a pivotal role in new product Introduction and production yield improvement. In this full time role, you'll report to our Director Foundry Technology. Our Foundry Technology group is dedicated to new products introduction and to transfer to our OSAT's, and your contributions will be instrumental in the New product development and Revenue. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Collaborate with foundries & internal teams on yield issue investigation and resolution Execute tapeouts to foundries Work with supply chain team on wafer WIP management. Work with design & CAD team on technology enablement. Qualifications S/M.S in Electrical Engineering or equivalent experience. Foundry technology experience especially experience with TSMC Yield improvement experience Knowledge in FinFet technology is a plus Knowledge in BCD technology is a plus Ability to learn and solve problems. Comfortable with collaboration, open communications and reaching across functional borders. About Rambus Rambus is a global company that makes

MTS Verification Engineering Marseille, UNAVAILABLE, FR Overview Rambus, a premier chip, and silicon IP provider, is seeking to hire an exceptional mid-level Design and Verification Engineer to join our PHY integration team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL Design and Verification activities related to PCIe Controller Soft IP development and PHYs integrations, on leading-edge PCI-Express and CXL controller technologies. This is a Full Time position. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work if you are located in Sofia. Responsibilities Verilog RTL design in order to integrate different IPs together such as PCIe IP with vendor PHY module Verifying the IP integration with dedicated simulation environment Development and support test cases of different verification environments Support worldwide customers on the IP integration Get familiar to existing verification process, propose improvements Maintain the traceability from the customer specification or the product specification to the architecture and verification results. Track and maintain verification productivity metrics Reporting periodically on progress and difficulties Qualifications "Can Do" Attitude Bachelor or Master's degree in Electronics Engineering, Computer Science, or related disciplines Strong analytical and problem-solving skills Excellent interpersonal skills Open for traveling abroad Work in international organization and specially with teams in France, USA, Taiwan and India Because Rambus operates internationally, very good English is important for

Sr Mgr Validation Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Validation Manager to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The Validation Manager is a Full-Time position and the candidate will manage and cooperate with the team to validate and characterize the product to deliver high-quality buffer chip products. The candidate is required to have experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts. Location(s): Atlanta, GA; San Jose, CA; Responsibilities Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, and procurement experts Own, develop and continuously adapt and improve validation methodologies and technologies to continuously improve design validation coverage and time-to-market Partner with Design, Architecture, Verification, and Operation teams to deliver high-quality buffer chip products Work with external partners in sourcing test equipment, PCB manufacturing and assembly. Manage bench validation team to execute bench validation and characterization of memory buffer chips. Hands-on execution bench validation and characterization, and software development for lab automation. Qualifications Bachelors or M.S. degree in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5. Prior experience in simulating high speed memory (DDR4, DDR5)

Director of Marketing, Memory Controllers San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Director of Product Marketing, Memory Controller IP to join our Silicon IP Marketing team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Director of Product Marketing, Memory Controller IP, you'll play a pivotal role in owning outbound marketing and go-to-market (GTM) strategy for Memory Controller product lines, including HBM, LPDDR, and others. This leader translates deep technical capabilities into clear value propositions, positioning, and sales-ready assets, drives product launches, and enables Sales/FAE teams to win design-ins. The role partners tightly with Product Management and Engineering throughout the lifecycle, including being a highly valued voice in product roadmaps. In this full-time role, you'll report directly to our VP of Marketing, SIP. Our Product Marketing group is dedicated to increasing the visibility, competitiveness and overall revenue of our Silicon IP products, and your contributions will be instrumental in growing mindshare of our Memory Controller IP products within our customer base. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Outbound Marketing & Go-to-Market (GTM) Ownership Own and execute outbound marketing for

Sr Package Design Engineer Taipei, UNAVAILABLE, TW Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Package Design Engineer to join our Package Engineering team in Taiwan. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. This is a full-time position reporting to the Director of Package Engineering. As a Senior Package Design Engineer, you will be responsible for supporting the design and layout of new products from early concept to tape out, focusing primarily on several elements that enable high-yielding, low defectivity production. The Senior Package Design Engineer will have the opportunity to work with multiple package technologies and outsourced suppliers to ensure manufacturing readiness for the Rambus product portfolio. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Drive early chip-package co-design and development of bump and ball map. Own layout of package types such as FCCSP, FCBGA, FCQFN, WLCSP, QFN. Collaborate with multiple cross-functional teams (Chip Design, SI/PI, Packaging) Analyze cost/performance/reliability trade-offs to complete layout of new products and test chips. Interact with OSAT partners and substrate/leadframe suppliers for design reviews and execution. Continuous improvement of package design workflow and unified package design guidelines. Assist with model creation for thermo-mechanical

Tech Dir Applications Engineering Gangnam-gu, Seoul, UNAVAILABLE, KR Overview Seeking an experienced applications engineer with DRAM and failure analysis expertise to support international customers of Rambus DDR4 and DDR5 memory interface chips in South Korea and Asia. Analyze and debug complex technical issues involving DRAM, memory interface chips, DIMM, server and BIOS operation and interaction. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Analyze and debug complex technical issues involving server memory and manage customer issues to a satisfactory conclusion. Support technical qualification of new chip designs to secure customer design wins. Assist with validation and debug of new memory interface chips for DDR5 servers. Collect and analyze signal integrity data at the system level. Conduct failure analysis and prepare failure analysis and 8D reports. Gather customer technical feedback and communicate to Marketing and Engineering teams. Present technical updates to customers and company management in writing and verbally via quality presentations. Prepare technical documentation such as datasheets, user guides and application notes. Qualifications Familiar with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers. Good understanding of signal integrity issues at clock rates of 3 GHz and above. Experience with power management and I2C/I3C serial interfaces. Extensive experience with probing, using high speed oscilloscopes and other lab equipment. History of using fundamental root cause techniques (fishbone,