Sr Principal Signal Integrity Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Sr Principal Signal Integrity Engineer Shanghai, UNAVAILABLE, CN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SPE Signal Integrity Engineer to join our Memory Interface Chip business unit in Shanghai, China . Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a SPE Signal Intergity Engineer, the candidate will be reporting to the VP Engineering and is a Full position. The candidate will work within our SI/PI team on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speeds up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed Qualifications Solid background in SI/PI and package design to provide technical leadership to the team Strong interpersonal skill to keep the team motivated and focused MS or PhD

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.