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Rambus INC

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  • Director of Marketing, Memory Controllers

    San Jose, CA, US

    unspecified $187K-$348K

    Director of Marketing, Memory Controllers San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Director of Product Marketing, Memory Controller IP to join our Silicon IP Marketing team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Director of Product Marketing, Memory Controller IP, you'll play a pivotal role in owning outbound marketing and go-to-market (GTM) strategy for Memory Controller product lines, including HBM, LPDDR, and others. This leader translates deep technical capabilities into clear value propositions, positioning, and sales-ready assets, drives product launches, and enables Sales/FAE teams to win design-ins. The role partners tightly with Product Management and Engineering throughout the lifecycle, including being a highly valued voice in product roadmaps. In this full-time role, you'll report directly to our VP of Marketing, SIP. Our Product Marketing group is dedicated to increasing the visibility, competitiveness and overall revenue of our Silicon IP products, and your contributions will be instrumental in growing mindshare of our Memory Controller IP products within our customer base. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Outbound Marketing & Go-to-Market (GTM) Ownership Own and execute outbound marketing for

  • Senior Design Verification Engineer - PCI-Express Controller IP

    SOFIA, UNAVAILABLE, BG

    unspecified Salary not disclosed

    Senior Design Verification Engineer - PCI-Express Controller IP SOFIA, UNAVAILABLE, BG Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional mid tosenior-level individual contributor Design Verification Engineer to join our PCIe Express IP Products team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL Verification activities related to PCIe Controller SoftIP development, on leading-edge PCI-Express and CXL controller technologies. This is a Full Time position, reporting to the local onsite Verification management. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work. Responsibilities Duties in this position will include: Testbench and test sequence development for verification of new controller technologies and features Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design Development & support of Verification environment scripting and capabilities Qualifications Bachelors Degree or above in EE/CS, at least 5-7 years prior experience with HDL logic Design-Verification SystemVerilog and/or UVM testbench, Verilog/SystemVerilog logic design, /RTL familiarity/project work Pre-existing Experience / familiarity with one or more I/O controller technologies such as PCI-Express, is highly desireable Working experience with Python and TCL scripting languages preferred About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP

  • Digital IC Design Engineer

    San Jose, CA, US

    hybrid $98K-$183K

    Digital IC Design Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional MTS Digital Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Work with analog/digital design team for new product development Responsible for RTL coding, functional simulation, analog-block Verilog model, post-pr simulation Support bench test, support ATE test Support chip bringing-up, debugging, failure analysis, characterizations and product release efforts Qualifications Master degree or above in EE or related field At least 3 years of digital IC design experience Experience in the area listed below: Embedded SRAM/OTP/Efuse/MTP controller Design for test for digital block, analog block Communication bus such as I2C/I3C/SPI/AHB/APB Familiar to schematic editor Being Familiar to mixed signal design and backend is a plus Mass product experience is a plus Self-motivated and proactive Good communication skills and a strong team player About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience,

  • Sr. Principal Verification Engineer

    San Jose, CA, US

    hybrid $170K-$315K

    Sr. Principal Verification Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SPE Verification Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Understand the architecture of the chip and functional blocks. Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures. Create testplan and develop test cases/sequences in UVM. Debug functional issues in the DUT based on the good understanding of the architectural specification. Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project. Qualifications MSEE/BSEE, CS or related field 7-10+ years experience Proficient in Verilog, systemverilog and UVM. Familiar with Linux environment and the industry's prevailing EDA tools. Have better understanding of Verification methodology and concepts. Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release. Have excellent communication skills (both written and oral) and cross-team/function collaboration capability. Experienced in code coverage and functional coverage closure. Strong problem-solving skills. About Rambus Rambus is a global company that makes

  • Sr Principal Signal Integrity Engineer

    Shanghai, UNAVAILABLE, CN

    unspecified Salary not disclosed

    Sr Principal Signal Integrity Engineer Shanghai, UNAVAILABLE, CN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SPE Signal Integrity Engineer to join our Memory Interface Chip business unit in Shanghai, China . Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a SPE Signal Intergity Engineer, the candidate will be reporting to the VP Engineering and is a Full position. The candidate will work within our SI/PI team on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speeds up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed Qualifications Solid background in SI/PI and package design to provide technical leadership to the team Strong interpersonal skill to keep the team motivated and focused MS or PhD

  • Lead MTS Analog Engineering

    San Jose, CA, US

    hybrid $133K-$246K

    Lead MTS Analog Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead MTS Analog Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Primary focus will be the products IO ESD/LU/EOS area, design & maintain the centralized ESD/LU/EOS design across multiple products. Create Chip/block level floorplan and work with mask designer to complete layout. Work with package engineering to create bonding diagram. Ownership of Analog/Mixed signal designs at chip and/or block level Chip level integration Work closely with Digital team to define analog/digital interface. Design, simulate and characterize analog/mixed signal circuits (e.g. Bandgap, Bias, LDO, IO, DC-DC BUCK, etc). Create and maintain test documents for test and validation engineering Work with the Lab/Validation team for test plan, silicon bring up and characterization Work closely with cross functional teams from different geographies and time zones to ensure engagement and execution Other responsibilities include design documentation and post silicon activity support Qualifications Deep understanding the process device ESD/LU/EOS. Deep understanding ERC/DRC/LVS. Competent in using fast simulator (CustomSim, XPS, AMS) for

  • Sr Mgr Validation Engineering

    San Jose, CA, US

    unspecified $162K-$300K

    Sr Mgr Validation Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Validation Manager to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The Validation Manager is a Full-Time position and the candidate will manage and cooperate with the team to validate and characterize the product to deliver high-quality buffer chip products. The candidate is required to have experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts. Location(s): Atlanta, GA; San Jose, CA; Responsibilities Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, and procurement experts Own, develop and continuously adapt and improve validation methodologies and technologies to continuously improve design validation coverage and time-to-market Partner with Design, Architecture, Verification, and Operation teams to deliver high-quality buffer chip products Work with external partners in sourcing test equipment, PCB manufacturing and assembly. Manage bench validation team to execute bench validation and characterization of memory buffer chips. Hands-on execution bench validation and characterization, and software development for lab automation. Qualifications Bachelors or M.S. degree in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5. Prior experience in simulating high speed memory (DDR4, DDR5)

  • SPE Applications/Validation Engineering

    San Jose, CA, US; Johns Creek, GA, US

    unspecified $158K-$293K

    SPE Applications/Validation Engineering San Jose, CA, US; Johns Creek, GA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr Principal Applications Engineer with DRAM and failure analysis expertise to analyze and debug complex technical issues involving DRAM, memory interface chips, DIMM, server and BIOS operation and interaction. This individual will support international customers of Rambus DDR4 and DDR5 memory interface chips in South Korea and Asia. You will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Analyze and debug complex technical issues involving server memory and manage customer issues to a satisfactory conclusion. Support technical qualification of new chip designs to secure customer design wins. Assist with validation and debug of new memory interface chips for DDR5 servers. Collect and analyze signal integrity data at the system level. Conduct failure analysis and prepare failure analysis and 8D reports. Gather customer technical feedback and communicate to Marketing and Engineering teams. Present technical updates to customers and company management in writing and verbally via quality presentations. Prepare technical documentation such as datasheets, user guides and application notes. Qualifications Familiar with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers.

  • Digital Design Engineer - New College Grad

    San Jose, CA, US

    hybrid $98K-$183K

    Digital Design Engineer - New College Grad San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional MTS Digital Design Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Work with analog/digital design team for new product development Responsible for RTL coding, functional simulation, analog-block Verilog model, post-pr simulation Support bench test, support ATE test Support chip bringing-up, debugging, failure analysis, characterizations and product release efforts Qualifications Master degree or above in EE or related field Experience in the area listed below: Embedded SRAM/OTP/Efuse/MTP controller Design for test for digital block, analog block Communication bus such as I2C/I3C/SPI/AHB/APB Familiar to schematic editor Being Familiar to mixed signal design and backend is a plus Mass product experience is a plus Self-motivated and proactive Good communication skills and a strong team player About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider

  • SPE Signal Integrity Engineer

    Johns Creek, GA, US; San Jose, CA, US; San Jose, UNAVAILABLE, US; Bangalore, UNAVAILABLE, IN; UNAVAILABLE, UNAVAILABLE, Seoul

    unspecified $134K-$249K

    SPE Signal Integrity Engineer Johns Creek, GA, US; San Jose, CA, US; San Jose, UNAVAILABLE, US; Bangalore, UNAVAILABLE, IN; UNAVAILABLE, UNAVAILABLE, Seoul Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU's engineering team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed

  • Technical Director Validation

    Johns Creek, GA, US

    unspecified $161K-$298K

    Technical Director Validation Johns Creek, GA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Technical Director Validation Engineer to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The Technical Director Validation Engineer is a Full-Time position and the candidate will work in the lab to automate data collection and provide framework to develop validation environment to check system performance and specification compliance. The candidate is required to have experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Lab bring-up and validation of high-speed memory buffer semiconductor products. Develop test methodologies for validating silicon designs against specifications. Develop scripts for automating lab equipment and for analyzing lab data. Lead validation tasks on bench planning, preparation, characterization execution, methodology improvements. Work with silicon design teams to develop experiments, drive data collection, and present results analysis. Provide inputs to FPGA, system, and PCB design requirements. Support Applications Team in understanding and resolving customer issues. Qualifications Experience in Bench testing and characterization of high speed and/or memory IO devices, exposure to DDRx characterization is preferable.

  • Lead MTS Program Management

    Rotterdam, UNAVAILABLE, NL; Vught, UNAVAILABLE, NL; Montreal, UNAVAILABLE, CA

    unspecified Salary not disclosed

    Lead MTS Program Management Rotterdam, UNAVAILABLE, NL; Vught, UNAVAILABLE, NL; Montreal, UNAVAILABLE, CA Overview We are seeking an experienced Program Manager with a strong technical foundation and a proven track record of delivering complex, multi‑disciplinary programs. In this role, you will lead cross‑functional initiatives, manage program roadmaps, and ensure successful execution from concept to completion. You will work closely with engineering, product management, and cross‑region stakeholders to drive alignment, remove roadblocks, and keep programs running smoothly. This role is based in either our Montreal office or our Netherlands locations. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Lead and manage end‑to‑end program execution across multiple engineering teams. Develop and maintain program plans, schedules, milestones, and metrics. Proactively identify risks, dependencies, and resource gaps, and drive mitigation plans. Facilitate effective communication across engineering, product, quality, and operations teams. Drive cross‑functional alignment on requirements, scope, timelines, and deliverables. Report program status, progress, and risks to leadership and key stakeholders. Continuously improve program management processes and operational efficiency. Qualifications 5 to 10 years of experience as a Program Manager in a technical environment. Engineering degree (Electrical, Computer, Mechanical, Software, or related). Demonstrated experience managing complex technical programs with multiple stakeholders. Strong communication, leadership, and problem‑solving skills. Ability to work effectively across global teams and time zones. Preferred Qualifications (Nice to Have) Experience in the

  • SMTS Verification Engineering

    Bangalore, KA, IN

    unspecified Salary not disclosed

    SMTS Verification Engineering Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SMTS Verification Engineer to join our Memory Interface chips team in Bangalore . In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a SMTS Engineer, you'll play a pivotal role in (DDR Verification, starting from understanding the design till Verification sign-off, and also to support the Validation team post-tapeouts ). In this full time role, you'll report directly to our Director. Our MIC team is dedicated to produce high speed DDR products at a high quality to meet the industry requirements, and your contributions will be instrumental in closing the Verification requirements of these products. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work Responsibilities Understand the product requirements from the specifications and beyond Planning and execution to meet the verification sign-off criteria Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system using UVM methodology Guide and mentor the team to meet the sign-off requirements Work with architects, designers and post-silicon teams Qualifications Bachelor's or Master's degree in Electronics with 5+ years of relevant experience Expertise in System verilog and UVM Strong debugging

  • MTS Analog Engineering

    Bangalore, KA, IN

    unspecified Salary not disclosed

    MTS Analog Engineering Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional MTS Engineer Analog Design to join our memory interface chip design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a MTS Analog Engineer - Analog Design, the candidate will be reporting to Sr Manager Engineering and is a Full-Time position. The candidate will be leading the analog mixed signal circuit design activities for high-performance mixed signal chip products. Rambus memory interface chips team delivers the most advanced chipset solutions for server memory sub-system. This role gives opportunities to invent solutions to improve performance of next generation high-performance mixed signal products and learnings opportunities working through all the phases of chip product design all the way from concept to volume production. Responsibilities Ownership of Analog/Mixed designs at chip and/or block level. Define optimal architectures to achieve competitive product specifications. Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, LDO, PLL, DLL, PI circuits). Create high level models for design tradeoff analysis and behavior model for verification simulations. Create floorplan and work with layout team to demonstrate post extraction performance. Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow. Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion. Participate and drive post silicon validation, debug,

  • PE Signal Integrity

    Bangalore, KA, IN

    hybrid Salary not disclosed

    PE Signal Integrity Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PE Signal Integrity to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities . Qualifications Solid background in SI/PI. B.E/Btech/MS/Mtech in Electronics/Electrical Engineering with 8+ years of industry experience. Strong theoretical background and understanding in EM and transmission line theory is a must. Solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required. Good understanding of crosstalk, Jitter and PDN concepts. Must understand package and PCB design. Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required. Exposure to commercial EDA tools such as ADS, HFSS, Q3D, Siwave, Hspice etc. Familiarity with Totem is a strong plus. Some exposure to ATE is desired, but not mandatory. Good to have experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc. Decent writing and presentation skills are essential as well as good communication skills to work with cross-functional teams. Must be an innovative, self-motivated and a team player. About Rambus Rambus is a global company that makes industry-leading memory interface chips

  • SMTS Foundry Technology

    Taipei, UNAVAILABLE, JP

    unspecified Salary not disclosed

    SMTS Foundry Technology Taipei, UNAVAILABLE, JP Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SMTS Foundry Technology to join our Operations Engineering team in Taiwan. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a SMTS Foundry Technology, you'll play a pivotal role in new product Introduction and production yield improvement. In this full time role, you'll report to our Director Foundry Technology. Our Foundry Technology group is dedicated to new products introduction and to transfer to our OSAT's, and your contributions will be instrumental in the New product development and Revenue. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Collaborate with foundries & internal teams on yield issue investigation and resolution Execute tapeouts to foundries Work with supply chain team on wafer WIP management. Work with design & CAD team on technology enablement. Qualifications S/M.S in Electrical Engineering or equivalent experience. Foundry technology experience especially experience with TSMC Yield improvement experience Knowledge in FinFet technology is a plus Knowledge in BCD technology is a plus Ability to learn and solve problems. Comfortable with collaboration, open communications and reaching across functional borders. About Rambus Rambus is a global company that makes

  • SMTS Reliability Engineering

    Chupei City, UNAVAILABLE, TW

    unspecified Salary not disclosed

    SMTS Reliability Engineering Chupei City, UNAVAILABLE, TW Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Reliability Engineer to join our Reliability Engineering team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Sr Reliability Engineer, the candidate will be reporting to the Director of Reliability Engineering and is a Full-Time position. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Own Ongoing Reliability Monitoring for production, task covers from ORM plan, coordinating test, data analysis, to final ORM report. Drive failure analysis to root causes and implementation of corrective actions by interacting with cross-function teams, design, validation, packaging, PE/TE, etc. Collaborate with foundries and package houses (OSATs) to assess, characterize, and improve product quality and reliability Reviewing and understanding reliability test results and making appropriate engineering judgement and decisions based on data, and driving appropriate action, Qualifications S/M.S in Electrical Engineering, Physics, Material Science, or equivalent experience. Experience in any one of the following semiconductor IC relevant fields, Quality, Reliability, Process, Validation, PE/TE etc. familiar with JEDEC qualification standards is a plus. Excellent interpersonal communication and writing skills while interacting with suppliers, customers, and internal staff. Ability to independently learn and collaborate for problem-solving.

  • Hardware Design Engineer

    Hillsboro, OR, US

    hybrid $107K-$198K

    Hardware Design Engineer Hillsboro, OR, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Design architecting and trade-off analysis RTL coding and verification Memory Controller + PHY integration and verification Customer delivery and support Qualifications Strong System Verilog/Verilog RTL design expertise Questa/Incisive/VCS simulator experience Python/Perl/Tcl scripting experience Significant ASIC and/or FPGA design experience Ability to learn quickly and work independently Solid communication and project management skills 5+ years of logic design experience BSEE Definite Plus: ASIC synthesis, timing constraint, CDC/RDC experience Verification experience Memory (HBM, GDDR, LPDDR, DDR) expertise AMBA AXI or CHI design experience Located in the Hillsboro, Oregon area Training: Provided as needed About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our

  • Lead Sourcing Analyst

    San Jose, CA, US

    unspecified $96K-$178K

    Lead Sourcing Analyst San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Sourcing Analyst to join our Memory Interface Chip team in San Jose, CA or Taiwan. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Lead Sourcing Analyst, the candidate will be reporting to the Director Sourcing and is a Full Time position. This role is responsible for defining and implementing all aspects of current and long-term sourcing strategies to effectively source foundry and OSAT that meet customer expectations of supply, quality, technology, and cost. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Responsibilities:· Supplier management; own commercial interface & supplier negotiations with key suppliers· Monitor supplier performance & KPI's including supply, cost, quality, and technology· Project management; drive projects as both project leader and/or member supporting strategic initiatives· Develop and maintain cost projection and perform data analysis that can be leveraged in negotiation and sourcing strategy· Lead mid-long term planning activities and actively seek opportunities for process improvements· Drive and sustain effective communication with internal and external partners Qualifications Qualifications:· 10+ years of experience to manage semiconductor related materials, suppliers, and have interactions with ASIC houses, fabless, OEM,

  • Tech Dir Applications Engineering

    Gangnam-gu, Seoul, UNAVAILABLE, KR

    hybrid Salary not disclosed

    Tech Dir Applications Engineering Gangnam-gu, Seoul, UNAVAILABLE, KR Overview Seeking an experienced applications engineer with DRAM and failure analysis expertise to support international customers of Rambus DDR4 and DDR5 memory interface chips in South Korea and Asia. Analyze and debug complex technical issues involving DRAM, memory interface chips, DIMM, server and BIOS operation and interaction. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Analyze and debug complex technical issues involving server memory and manage customer issues to a satisfactory conclusion. Support technical qualification of new chip designs to secure customer design wins. Assist with validation and debug of new memory interface chips for DDR5 servers. Collect and analyze signal integrity data at the system level. Conduct failure analysis and prepare failure analysis and 8D reports. Gather customer technical feedback and communicate to Marketing and Engineering teams. Present technical updates to customers and company management in writing and verbally via quality presentations. Prepare technical documentation such as datasheets, user guides and application notes. Qualifications Familiar with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers. Good understanding of signal integrity issues at clock rates of 3 GHz and above. Experience with power management and I2C/I3C serial interfaces. Extensive experience with probing, using high speed oscilloscopes and other lab equipment. History of using fundamental root cause techniques (fishbone,