SPE Signal Integrity Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

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Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$134K-$249K not verified - source not recorded; timestamp not recorded

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

U.S. benchmark only; posted salary is not compared across countries or currencies.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

SPE Signal Integrity Engineer Johns Creek, GA, US; San Jose, CA, US; San Jose, UNAVAILABLE, US; Bangalore, UNAVAILABLE, IN; UNAVAILABLE, UNAVAILABLE, Seoul Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU's engineering team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.