Sr. Principal Verification Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$170K-$315K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$55,390 U.S. median for this role

Projected growth (BLS Employment Projections)

-0.1% - Decline

338% above the BLS role benchmark for teaching and education aggregate.

Posted salary is far from this role benchmark; treat it as low confidence.

Matched to SOC 25-2021 - Teaching and Education aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Teaching Education From the posting source checked Jun 20, 2026

Seniority

Staff Plus From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Sr. Principal Verification Engineer San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional SPE Verification Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Understand the architecture of the chip and functional blocks. Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures. Create testplan and develop test cases/sequences in UVM. Debug functional issues in the DUT based on the good understanding of the architectural specification. Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project. Qualifications MSEE/BSEE, CS or related field 7-10+ years experience Proficient in Verilog, systemverilog and UVM. Familiar with Linux environment and the industry's prevailing EDA tools. Have better understanding of Verification methodology and concepts. Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release. Have excellent communication skills (both written and oral) and cross-team/function collaboration capability. Experienced in code coverage and functional coverage closure. Strong problem-solving skills. About Rambus Rambus is a global company that makes

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.