Sr Mgr Validation Engineering

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$162K-$300K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

98% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Sr Mgr Validation Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Validation Manager to join our Memory Interface Chip business unit. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. The Validation Manager is a Full-Time position and the candidate will manage and cooperate with the team to validate and characterize the product to deliver high-quality buffer chip products. The candidate is required to have experience with processor-memory interfaces, including DDR topologies and protocols, as well as high-speed signaling, including signal integrity and power integrity concepts. Location(s): Atlanta, GA; San Jose, CA; Responsibilities Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, and procurement experts Own, develop and continuously adapt and improve validation methodologies and technologies to continuously improve design validation coverage and time-to-market Partner with Design, Architecture, Verification, and Operation teams to deliver high-quality buffer chip products Work with external partners in sourcing test equipment, PCB manufacturing and assembly. Manage bench validation team to execute bench validation and characterization of memory buffer chips. Hands-on execution bench validation and characterization, and software development for lab automation. Qualifications Bachelors or M.S. degree in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5. Prior experience in simulating high speed memory (DDR4, DDR5)

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.