Lead MTS Analog Engineering

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$133K-$246K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

63% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Lead MTS Analog Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead MTS Analog Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Primary focus will be the products IO ESD/LU/EOS area, design & maintain the centralized ESD/LU/EOS design across multiple products. Create Chip/block level floorplan and work with mask designer to complete layout. Work with package engineering to create bonding diagram. Ownership of Analog/Mixed signal designs at chip and/or block level Chip level integration Work closely with Digital team to define analog/digital interface. Design, simulate and characterize analog/mixed signal circuits (e.g. Bandgap, Bias, LDO, IO, DC-DC BUCK, etc). Create and maintain test documents for test and validation engineering Work with the Lab/Validation team for test plan, silicon bring up and characterization Work closely with cross functional teams from different geographies and time zones to ensure engagement and execution Other responsibilities include design documentation and post silicon activity support Qualifications Deep understanding the process device ESD/LU/EOS. Deep understanding ERC/DRC/LVS. Competent in using fast simulator (CustomSim, XPS, AMS) for

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.