Hardware Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$107K-$198K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

31% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Hardware Design Engineer Hillsboro, OR, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Design architecting and trade-off analysis RTL coding and verification Memory Controller + PHY integration and verification Customer delivery and support Qualifications Strong System Verilog/Verilog RTL design expertise Questa/Incisive/VCS simulator experience Python/Perl/Tcl scripting experience Significant ASIC and/or FPGA design experience Ability to learn quickly and work independently Solid communication and project management skills 5+ years of logic design experience BSEE Definite Plus: ASIC synthesis, timing constraint, CDC/RDC experience Verification experience Memory (HBM, GDDR, LPDDR, DDR) expertise AMBA AXI or CHI design experience Located in the Hillsboro, Oregon area Training: Provided as needed About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.