PE Physical Design

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$66,396 U.S. median for this role

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

PE Physical Design Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Own end-to-end physical implementation for major IP blocks and/or full-chip designs. Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus). Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability. Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements. Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones. Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability. Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement. Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results Qualifications Must have minimum Bachelors degree in EE/ECE (degree's related to electronics) from a reputed institute. Must have at least 10 years of experience, out of

Read the full description at careers-rambus.icims.com. FewerJobs shows a preview and links to the original posting.