Matx jobs

Hardware System Electrical Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. About the Role: We are looking for a Hardware Systems Engineer to join our Hardware Systems team. In this role, you will take full ownership of defining, designing, and validating compute trays, boards, and interconnects for our rack-scale AI data center platform. You will work across control plane, data plane, and management plane functionality, playing a pivotal role in driving power efficiency, scalability, reliability, and system performance at scale What You'll Do Here: - Full ownership of board design, specifications, schematic design, verification and reliability test plan for our AI compute boards - Design and capture schematic and work with layout engineers to release Gerber files - Collaborate with cross-functional teams, such as thermal, mechanical, SIPI, ASIC, platform software and manufacturing diagnostic software teams. - Bring up boards and debug hardware issues in the lab - Support platform and manufacturing tests - Collaborate with JDM Who You Are: - At least 10

Hardware System Diagnostic Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. We are looking for a Diagnostic Engineer to join our Hardware System team. The successful candidate will be responsible for defining, designing, and owning the end-to-end diagnostics test suite for manufacturing, debugging and deployment of our rack-scale AI data center product. This role is crucial for collaborating with JDM to ensure high manufacturing yield and robust products from manufacturing to customer deployment. What You'll Do Here - Own the end-to-end diagnostics test suite for accelerator boards and racks - Develop diagnostic tools covering the AI chip, PCIe, HBM, power, and thermal - Define test coverage and pass/fail criteria for manufacturing screening - Enable JDM/ODM partners with documentation, tooling, and hands-on debug support - Support partners technically through NPI and production ramp phases - Triage and root-cause manufacturing test escapes and field failures - Build and maintain CI/CD infrastructure for the diagnostics software stack - Track quality metrics - yield, test coverage, defect

Software Engineer - Compiler Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. We primarily use the Rust programming language . What You'll Do Here - Design and implement compilers tailored for our proprietary hardware architecture - Provide valuable insights and guidance on hardware architecture, offering a compiler author's perspective - Focus on midend and backend development Who You Are - Bachelor of Computer Science or equivalent degree - Possess outstanding software engineering skills with a focus on efficiency and performance - Possess experience in compiler algorithms, demonstrating proficiency in areas such as register allocation, instruction scheduling, instruction selection, and loop optimizations - This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have - Familiarity with optimizing software at a low level, including expertise in parallelism SIMD programming, C, or assembly-level optimization, and familiarity with GPU kernels - Excellent ability to deal with a dynamic environment and anticipate downstream changes - Be comfortable with mid level optimizer and and be willing to make downstream changes - Familiarity with ML models such as Transformers. - Interest in building tools that people use - Interest in languages, Rust maintenance, and library development Compensation The US base salary

ASIC/SOC Silicon Verification Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon verification engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Contribute to MatX's verification methodology with a scalable solution across blocks, subsystems, fullchip and system-level validation - Own portions of verification execution at subsystem and chip-level and create testbenches, tests and related artifacts to achieve structural and functional coverage closure - Plan and drive intermediate and sign-off reviews on verification test plans, execution progress and verification closure towards various silicon milestones including design freeze and tapeout Who You Are - Concept-to-silicon experience in driving verification from an architecture and/or design specification to production silicon - Experience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for verification and silicon modeling - Production experience with advanced verification methodologies such as UVM, assertion-based verification (ABV); experience and comfort with formal and simulated verification are required - Production experience with creating portable tests and drivers for verification that apply to silicon validation and post-silicon debug - Strong understanding of silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs,

System Software Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking System Software Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. As an System Software Engineer reporting to our Systems Software Lead, you'll contribute to the System Software Team. You'll join a talented group of engineers helping us to create best-in-class silicon for high-performance and sustainable GenAI. As part of a small team, you'll help see your ideas come to life and see the impacts of your work. What You'll Do Here - Work closely with the architecture teams, silicon design teams and other software/firmware teams to architect, design, and implement scalable and high-performance system software components, including device drivers in Linux, low-level libraries and daemons - Deliver unit-tests for all software components being developed, including kernel level softwares - CPU/memory subsystem optimization for the host system stack - Write debug and performance monitoring utilities - Performance profiling, look for opportunities to reduce operating system overheads - Influence the design of next generations of accelerators, and the host system software stack - Design system software components to improve system observability, improve resiliency - Design and implement

Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. What You'll Do Here - Develop, support, and own hardware architecture throughout the product lifecycle - Deeply understand customer use cases, workload performance, and ML systems research - Produce requirements and architecture specifications - Estimate hardware area, timing, and power to inform architectural trade-offs - Collaborate closely with Research, Software, and Hardware teams - Interface with vendors and customers - Architectural Responsibilities May Include: - Parallel Compute: SIMD, Vector, VLIW, and other parallel execution models - Data Movement: Efficient storage and communication across memory and network fabrics - Distributed Systems: Workload mapping, bottleneck analysis, and scalable distributed systems Who You Are - Expertise in modern high-performance CPU, GPU, or AI accelerator architecture and hardware/software interactions - Experience analyzing and optimizing system performance using diverse tools and methodologies - Proficiency in programming and code optimization - Excellent writing skills - This is a hybrid role that will require you to work from our Mountain View, CA office 3

ASIC/SOC CAD Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow, including construction and sign-off - Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights - Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results - Work with EDA tool vendors to drive issues and enhancements to closure - Train and support flow users and resolve any issues they might face - Manage licenses, compute, and storage and optimize for efficiency and cost - May include some development and support of the front-end CAD flow Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise developing/using industry-standard ASIC tools and methodologies

Executive Operations Coordinator, Office of the CEO Mountain View, CA What MatX Is Building MatX is building cutting-edge AI infrastructure at the intersection of hardware and software, on a mission to make the world's best AI models run as efficiently as possible. We're growing fast, and our CEO's time is one of the most valuable resources in the company. This role exists to protect and multiply it. About This Role The Office of the CEO at MatX operates as a team of three: the CEO, his Chief of Staff, and you (reporting to the Chief of Staff). You'll own the operational surface area of this office, allowing the CoS and CEO to focus on company-wide strategy and operational decision-making. You'll turn calendaring, communications, and logistics into a multiplier for the CEO's impact on company outcomes. You'll learn how we work: how the CEO thinks and prioritizes, how the CoS works, and where the gaps are. You'll start filling those gaps on your own: drafting follow-up emails, figuring out next steps and who owns them during meetings, or proactively suggesting comms to address the themes you're hearing across the company. This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week, on Tuesday through Thursday What You'll Do Here - Calendar and time management. You own the CEO's schedule and use it to strategically spend his time. You'll learn company priorities, when he needs buffers, which "quick calls" are actually high-priority,

ASIC/SOC Silicon Physical Design Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII - Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) - Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout - Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL

Emulation Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. We're hiring a Senior/Staff Emulation Engineer to build the infrastructure, flows, and debug methodology behind our advanced connectivity SoCs. The role sits in the Emulation team, but the impact is broader: you'll create reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation. We're looking for a multi-disciplinary engineer with an out-of-the-box, can-do mindset - someone who sees a gap and builds the bridge, comfortable moving between RTL, software, tooling, system debug, and vendor flows. You don't need to be an expert in every area listed below. You do need a reuse-first mindset, strong software instincts, and the ability to learn quickly across boundaries. What You'll Do Here - Define and execute emulation strategy and test plans for complex connectivity SoCs. - Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu or Veloce. - Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and

SOC Intergration Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design. - Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL. - Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL. - Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL. - Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams. - Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements. - Provide technical support to package and board teams by defining SOC pin

AI Accelerator Silicon Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. MatX is seeking an AI Accelerator Compute Architect to help define the compute architecture for our next-generation GenAI accelerators. What You'll Do - Define the architecture for MatX's AI compute subsystem, including ISA, connectivity, memories, and control.. - Derive architectural requirements from AI use cases. - Conduct analytical and empirical performance analysis. - Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA. - Work through power, area, performance tradeoffs with stakeholders. - Support test plan reviews, first-silicon bring-up, and post-silicon debug. Who You Are - Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures. - Experience translating workloads into hardware architecture. - Solid microarchitecture fundamentals. - First-principles understanding of latency, throughput, utilization, and scalability. - Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs. - Programming, code optimization, or kernel-level performance analysis experience. -

Silicon Micro-Architect and RTL Designer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design - Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design - Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout - Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results Who You Are - Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon - 2 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows - Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed

Silicon Design-for-Test (DFT) Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes. What You'll Do Here - Design and develop functional test solutions for SERDES PHY , covering loopback, eye diagram characterization, and margin testing. - Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level. - Develop and maintain firmware loading flows for PHY bring-up and test - including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development. - Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE. - Execute DFT implementation and verification flows for block-level DFT insertion , including scan chain closure, ATPG pattern generation, and sign-off. - Support test escapes root cause analysis and drive continuous improvement of DFT coverage and test quality. Who You Are - Hands-on

Platform Technical Project Manager, Rack-Scale AI Sysytems Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. About the Role MatX is building next-generation AI infrastructure systems for high-performance datacenter workloads. We are looking for a Senior Platform TPM, Rack-Scale AI Systems to drive design-phase execution for our rack-scale platform. This role will coordinate cross-functional execution across rack architecture, accelerator board design, power delivery, thermal and liquid cooling, high-speed interconnect, firmware, diagnostics, test vehicles, system validation, and external CM/JDM partner engagement. You will work closely with Systems Engineering, hardware engineering, firmware, validation, supply chain, and external CM/JDM partners. What You'll Do Here - Drive the integrated execution plan for rack and board design from architecture through design release. - Own and maintain the design-phase master schedule across rack, board, power, thermal, interconnect, mechanical, firmware, diagnostics, validation, and supply-chain dependencies. - Coordinate execution across key platform workstreams, including board electrical/SI/PI readiness, rack power, liquid cooling, cable/optical interconnect, BMC/telemetry, diagnostics, test vehicles, PLM/BOM/ECO readiness, and external CM/JDM design

Senior UX Researcher Oakland, California, United States, AMER From Fivetran's founding until now, our mission has remained the same: to make access to data as simple and reliable as electricity. With Fivetran, customer data arrives in their warehouses, canonical and ready to query, with no engineering or maintenance required. We're proud that more organizations continue to leverage our technology every day to become truly data-driven. About the Role We are looking for a Senior UX Researcher to join our rapidly growing Product org. You will help shape the future of the Fivetran data pipeline platform for businesses large and small. Our ideal candidate has a balance of research rigor and business focus. We value those that hit the ground running, leading by example on projects and collaborating well cross-functionally. You will be diving deep into the daily lives of our customers and applying that understanding to everyday product design decisions. As you talk with our team, your portfolio should contain case studies that demonstrate strong storytelling skills, use of effective research methodologies, and clear impact of your previous work. Fivetran has a positive, diverse, and supportive culture. We appreciate Researchers who are curious, humble, think deeply, speak clearly, and thrive on collaboration and feedback. If this sounds like a good fit for you, send us a hello with links to your work and experience. On day one, this role will report to the Director of UX Research. This is a full-time position based in our Oakland, CA office. Our hybrid

Senior Software Engineer Australia - (Sydney) posted: Posted 3 Days Ago

Quantitative UX Researcher San Francisco, California, United States About the team The UX Research team is a small team with outsized impact across OpenAI. We sit at the intersection of users, product, and safety-helping ensure that powerful AI systems are built responsibly and grounded in real human needs. Our work informs critical product decisions across OpenAI. We partner closely with product, design, engineering, and leadership to bring clarity to complex questions-often in fast-moving spaces where norms and best practices are still being defined. This role is based in San Francisco, CA. We operate on a hybrid model with 3 days in the office each week and offer relocation assistance. In this role, you will: - Design and execute quantitative research across the product lifecycle, from foundational understanding to concept validation, prototyping, and usability evaluation. - Partner with product managers, designers, engineers, and data scientists to identify high-impact opportunities where quantitative insights can meaningfully shape product decisions. - Lead rigorous, customized studies that answer both strategic and tactical questions, using methods such as surveys, experiments, and behavioral data analysis. - Translate complex data into clear, actionable recommendations that drive alignment and decision-making across teams. - Apply strong survey methodology and statistical rigor to ensure findings are valid, reliable, and decision-ready. - Influence product direction through close cross-functional collaboration and clear, audience-appropriate storytelling. You might thrive in this role if you have: - 5+ years of experience working in user experience research, market research, data science, and/or a related field with a

Quantitative UX Researcher, Applied AI Solutions Seattle, Washington, USA We are seeking a Quantitative UX Researcher who is excited to help shape the future of AI-native business applications. This is an opportunity to influence product direction by helping teams understand how customers interact with AI-powered experiences and what drives adoption, trust, usability, and customer value. In this role, you will lead quantitative research that helps teams build, test, and learn faster. You will turn product questions into clear hypotheses, success metrics, well-designed studies, and actionable insights. Your work will help teams evaluate new ideas, improve existing experiences, and make better product decisions. This is a quant-first role with mixed-methods responsibilities as needed. We are looking for a researcher with strong skills in experimentation, analytics, behavioral analysis, and causal inference. You should be comfortable working in ambiguous, early-stage spaces and helping teams define how success should be measured for new AI-powered products. You will identify meaningful behavioral and attitudinal signals, measure product performance, and recommend improvements based on the evidence. Key job responsibilities - Lead quantitative and mixed-methods research for AI-powered products, including early-stage concepts and evolving customer experiences. - Own studies from end to end, including framing research questions, defining hypotheses, selecting methods, identifying measures, analyzing results, and communicating recommendations. - Design and run experiments, surveys, and behavioral analyses that help teams understand customer needs, product performance, and opportunities for improvement. - Define and track success metrics related to adoption, trust, usability, comprehension, and customer value in AI-powered experiences. -

UX Researcher, Quantitative Menlo Park, CA; New York, NY Our UX Research team is designing for the global spectrum of human needs, which requires us to deeply understand the behaviors of the people behind them. Our researchers tackle some of the most complex challenges to gain deeper insights into how people interact with each other and the world around them, and work collaboratively to contribute new ideas to products that impact the experiences of billions of people on a global scale. This job description represents different full-time roles across Meta. We use a variety of qualitative and quantitative methods to accomplish our goals, including surveys, focus groups, field studies, usability tests, and 1:1 interviews. We value a wide range of perspectives and stem from many different perspectives, approaches, experiences and backgrounds. We're looking for excellent communicators who are knowledgeable about research devoted to understanding people, and curious about the relationship between technology and society. They will also need to be comfortable in a fast-moving organization, open-minded about learning new research methods, committed to high-quality and rigorous research, and focused on influencing the future of Meta. Responsibilities: - Work closely with product and business teams to identify research topics - Act as a thought leader in the domain of research, while advocating for the people who could use our products - Design and execute end-to-end custom primary research using a wide variety of methods - Design studies that address both user behavior and attitudes - Ability to work independently and autonomously

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