AI Accelerator Silicon Architect

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

$120K-$275K From the posting source checked Jun 20, 2026

401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

69% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Staff Plus From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Company stage

Seed From the posting source checked Jun 20, 2026

Equity

Offered From the posting source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

AI Accelerator Silicon Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. MatX is seeking an AI Accelerator Compute Architect to help define the compute architecture for our next-generation GenAI accelerators. What You'll Do - Define the architecture for MatX's AI compute subsystem, including ISA, connectivity, memories, and control.. - Derive architectural requirements from AI use cases. - Conduct analytical and empirical performance analysis. - Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA. - Work through power, area, performance tradeoffs with stakeholders. - Support test plan reviews, first-silicon bring-up, and post-silicon debug. Who You Are - Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures. - Experience translating workloads into hardware architecture. - Solid microarchitecture fundamentals. - First-principles understanding of latency, throughput, utilization, and scalability. - Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs. - Programming, code optimization, or kernel-level performance analysis experience. -

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