ASIC/SOC Silicon Physical Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

$120K-$250K From the posting source checked Jun 20, 2026

401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

59% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Equity

Offered From the posting source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC/SOC Silicon Physical Design Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII - Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) - Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout - Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL

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