ASIC Design Engineer

Benefits

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Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

ASIC Design Engineer San Jose, California, US The application window is expected to close on: Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Contribute to the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Develop design and micro-architecture specifications and participate in technical design reviews. Collaborate closely with verification teams to resolve design issues and drive functional coverage closure. Work with physical design teams to address timing, synthesis, and place-and-route challenges. Debug and root-cause issues across simulation, system integration, and silicon bring-up environments. Contribute to post-silicon validation and lab bring-up to ensure successful silicon delivery. Minimum Qualifications Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience. Experience with at least

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