Silicon Micro-Architect and RTL Designer
MatX - Mountain View, CA
Posted May 19, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Salary
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- 401(k) match
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Schedule
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- Weekend work
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Application
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- Assessment
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- Deadline
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Where they hire
State eligibility is not yet verified.
About this role
Silicon Micro-Architect and RTL Designer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design - Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design - Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout - Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results Who You Are - Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon - 2 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows - Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed
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