ASIC/SOC CAD Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

$120K-$250K From the posting source checked Jun 20, 2026

401(k) match

Reported not verified - source URL not recorded; timestamp not recorded

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

59% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered From the posting source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC/SOC CAD Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow, including construction and sign-off - Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights - Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results - Work with EDA tool vendors to drive issues and enhancements to closure - Train and support flow users and resolve any issues they might face - Manage licenses, compute, and storage and optimize for efficiency and cost - May include some development and support of the front-end CAD flow Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise developing/using industry-standard ASIC tools and methodologies

Read the full description at job-boards.greenhouse.io. FewerJobs shows a preview and links to the original posting.