Matx jobs

Software Engineer - Simulators Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. We primarily use the Rust programming language . What You'll Do Here - Develop and maintain functional and performance models of our hardware - Develop tools and infrastructure to aid in efficient correlation, debug, and testing - Collaborate with model customers: architecture, verification/validation, compiler, and runtime teams - Contribute to architectural decisions and reviews - Investigate and implement performance optimizations Who You are - Bachelor of Computer Science or equivalent degree - Excellent software engineering skills, with a focus on maintainable performant - Strong foundation in computer architecture fundamentals - Excellent cross-functional communication skills - Rust experience AND/OR experience writing cycle-accurate simulators - This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have - Deep knowledge of Machine Learning Accelerator architectures - Experience with benchmarking and optimizing code - Familiar with processor, memory, and networking architectures - An understanding of Power, Performance, Cost tradeoffs Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation. -

Hardware System Electrical Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. About the Role: We are looking for a Hardware Systems Engineer to join our Hardware Systems team. In this role, you will take full ownership of defining, designing, and validating compute trays, boards, and interconnects for our rack-scale AI data center platform. You will work across control plane, data plane, and management plane functionality, playing a pivotal role in driving power efficiency, scalability, reliability, and system performance at scale What You'll Do Here: - Full ownership of board design, specifications, schematic design, verification and reliability test plan for our AI compute boards - Design and capture schematic and work with layout engineers to release Gerber files - Collaborate with cross-functional teams, such as thermal, mechanical, SIPI, ASIC, platform software and manufacturing diagnostic software teams. - Bring up boards and debug hardware issues in the lab - Support platform and manufacturing tests - Collaborate with JDM Who You Are: - At least 10

Software Engineer - Kernels Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. We primarily use the Rust programming language . What You'll Do Here - Design and optimize kernels that interface directly with our hardware - Work in partnership with our ML Research and Hardware Engineering teams - Provide expertise and guidance on hardware architecture from a programmer's perspective, ensuring seamless integration with the software stack Who You Are - Bachelor of Computer Science or equivalent degree - Experience optimizing software for specialized hardware, employing techniques such as parallelism, SIMD programming, C, assembly-level optimization, or GPU/CUDA programming - Language: at least one of assembly, C++, C, Zig, or Rust - This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have - Experience implementing kernels for ML models such as Transformers - Experience using and implementing distributed parallelism techniques such as AllReduce, AllToAll, data parallelism, tensor parallelism. - Familiarity with how compilers work Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation. - Early Career - $120,000

SOC Architect (Remote) Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next-generation AI-focused, server-class silicon. What You'll Do Here - Lead SoC architecture by translating Product Requirements Documents (PRDs) into SoC-level architectures in collaboration with subsystem architects and cross-functional teams - Define SoC architecture including memory, systems, interconnects, clocking, power, IP requirements, and system integration - Define system flows for power-up, boot, and recovery - Own PPA feasibility and drive power, performance, and area trade-offs with implementation teams - Own architectural specifications and documentation from definition through productization Who You Are - Industry experience in complex SoC architectures - Knowledge of memory systems and interconnect fabrics, including industry standards - Ability to define functional and PPA requirements from use cases - Sound architectural judgment in driving trade-off decisions - Excellent technical communication, documentation, and organizational skills - Experience collaborating across hardware, software, and third-party IP teams - Programming/scripting skills (verilog, bash, C/C++, python etc) Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.

Mechanical and Thermal Reliability Engineer Mountain View, CA What MatX Is Building Matx is developing advanced rack- and POD-level infrastructure systems to support next-generation high-performance computing and AI workloads. Our focus is on delivering highly reliable, thermally efficient, and scalable hardware solutions, including cutting-edge liquid cooling architectures and mechanical systems. We are building vertically integrated platforms that combine mechanical design, thermal management, packaging, and system-level engineering to ensure robust performance under extreme operating conditions. We are looking for engineers who are passionate about reliability engineering, system validation, and cross-functional product development. What You'll Do Here - Develop and execute reliability strategies and qualification plans for New Product Development (NPD) programs - Design and implement Design of Experiments (DOE) for material, process, and product validation - Perform reliability testing, evaluation, and qualification for mechanical and thermal systems - Lead qualification readiness assessments, including material readiness and test program validation - Conduct failure analysis and root cause investigations, and drive corrective and preventive actions (CAPA) during development. - Work on system-level reliability for: - Mechanical assemblies - High-speed connectors - Compute blade architectures - Evaluate and improve the reliability of liquid cooling systems, including: - Direct-to-chip (D2C) cooling - Rack and POD-level liquid cooling infrastructure - Collaborate with ODM, JDM, and CM partners on L6~L11 system testing and reliability validation - Develop reliability reports, risk assessments, and qualification documentation - Contribute to product validation processes and drive improvements in product quality and reliability Who You Are - 0-5 years of experience in

Software Engineer - Compiler Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. We primarily use the Rust programming language . What You'll Do Here - Design and implement compilers tailored for our proprietary hardware architecture - Provide valuable insights and guidance on hardware architecture, offering a compiler author's perspective - Focus on midend and backend development Who You Are - Bachelor of Computer Science or equivalent degree - Possess outstanding software engineering skills with a focus on efficiency and performance - Possess experience in compiler algorithms, demonstrating proficiency in areas such as register allocation, instruction scheduling, instruction selection, and loop optimizations - This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have - Familiarity with optimizing software at a low level, including expertise in parallelism SIMD programming, C, or assembly-level optimization, and familiarity with GPU kernels - Excellent ability to deal with a dynamic environment and anticipate downstream changes - Be comfortable with mid level optimizer and and be willing to make downstream changes - Familiarity with ML models such as Transformers. - Interest in building tools that people use - Interest in languages, Rust maintenance, and library development Compensation The US base salary

Hardware System Diagnostic Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. We are looking for a Diagnostic Engineer to join our Hardware System team. The successful candidate will be responsible for defining, designing, and owning the end-to-end diagnostics test suite for manufacturing, debugging and deployment of our rack-scale AI data center product. This role is crucial for collaborating with JDM to ensure high manufacturing yield and robust products from manufacturing to customer deployment. What You'll Do Here - Own the end-to-end diagnostics test suite for accelerator boards and racks - Develop diagnostic tools covering the AI chip, PCIe, HBM, power, and thermal - Define test coverage and pass/fail criteria for manufacturing screening - Enable JDM/ODM partners with documentation, tooling, and hands-on debug support - Support partners technically through NPI and production ramp phases - Triage and root-cause manufacturing test escapes and field failures - Build and maintain CI/CD infrastructure for the diagnostics software stack - Track quality metrics - yield, test coverage, defect

System Software Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking System Software Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. As an System Software Engineer reporting to our Systems Software Lead, you'll contribute to the System Software Team. You'll join a talented group of engineers helping us to create best-in-class silicon for high-performance and sustainable GenAI. As part of a small team, you'll help see your ideas come to life and see the impacts of your work. What You'll Do Here - Work closely with the architecture teams, silicon design teams and other software/firmware teams to architect, design, and implement scalable and high-performance system software components, including device drivers in Linux, low-level libraries and daemons - Deliver unit-tests for all software components being developed, including kernel level softwares - CPU/memory subsystem optimization for the host system stack - Write debug and performance monitoring utilities - Performance profiling, look for opportunities to reduce operating system overheads - Influence the design of next generations of accelerators, and the host system software stack - Design system software components to improve system observability, improve resiliency - Design and implement

Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. What You'll Do Here - Develop, support, and own hardware architecture throughout the product lifecycle - Deeply understand customer use cases, workload performance, and ML systems research - Produce requirements and architecture specifications - Estimate hardware area, timing, and power to inform architectural trade-offs - Collaborate closely with Research, Software, and Hardware teams - Interface with vendors and customers - Architectural Responsibilities May Include: - Parallel Compute: SIMD, Vector, VLIW, and other parallel execution models - Data Movement: Efficient storage and communication across memory and network fabrics - Distributed Systems: Workload mapping, bottleneck analysis, and scalable distributed systems Who You Are - Expertise in modern high-performance CPU, GPU, or AI accelerator architecture and hardware/software interactions - Experience analyzing and optimizing system performance using diverse tools and methodologies - Proficiency in programming and code optimization - Excellent writing skills - This is a hybrid role that will require you to work from our Mountain View, CA office 3

ASIC/SOC Silicon Verification Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon verification engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Contribute to MatX's verification methodology with a scalable solution across blocks, subsystems, fullchip and system-level validation - Own portions of verification execution at subsystem and chip-level and create testbenches, tests and related artifacts to achieve structural and functional coverage closure - Plan and drive intermediate and sign-off reviews on verification test plans, execution progress and verification closure towards various silicon milestones including design freeze and tapeout Who You Are - Concept-to-silicon experience in driving verification from an architecture and/or design specification to production silicon - Experience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for verification and silicon modeling - Production experience with advanced verification methodologies such as UVM, assertion-based verification (ABV); experience and comfort with formal and simulated verification are required - Production experience with creating portable tests and drivers for verification that apply to silicon validation and post-silicon debug - Strong understanding of silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs,

Technical Hardware/Semiconductor Recruiter Mountain View, CA MatX is on a mission to make the world's best AI models run as efficiently as possible-accelerating global progress in AI quality and accessibility. We are building cutting-edge AI infrastructure at the intersection of hardware and software, and our team is growing quickly. We are seeking a Technical Recruiter with deep experience in technical recruiting and a strong understanding of the Semiconductor, Hardware and AI landscape. This role will play a critical part in scaling our teams by owning key stages of the hiring process, delivering an exceptional candidate experience, and driving performance through reporting key metrics for talent acquisition to senior leadership and hiring teams. This position is ideal for someone who thrives in a fast-paced startup environment, partners effectively with a wide range of stakeholders, and brings both rigor and empathy to recruiting. You will have a direct impact on company growth and will help shape recruiting processes as MatX continues to scale. This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday What You'll Do Here - Hire for specialized Semiconductor and Hardware engineering roles that span product development cycle from architecture to various functional engineering roles, including design, validation, testability, silicon physical design, system hardware design, infrastructure-as-code, customer support, and product deployment - Previous experience recruiting for ASIC, SOC, Silicon Design, Silicon Architecture, Security and Verification highly preferred - Hire for specialized Semiconductor and Hardware

ASIC/SOC CAD Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow, including construction and sign-off - Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights - Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results - Work with EDA tool vendors to drive issues and enhancements to closure - Train and support flow users and resolve any issues they might face - Manage licenses, compute, and storage and optimize for efficiency and cost - May include some development and support of the front-end CAD flow Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise developing/using industry-standard ASIC tools and methodologies

Formal Verification Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. We build the full stack-from silicon and rack design through compilers, kernels, and ML models. We are seeking a Formal Verification Engineer to bring rigorous mathematical guarantees to our hardware and software at every layer of the stack. What You'll Do Here - Apply model checking and formal property verification to RTL blocks, memory subsystems, and interconnects, providing complete coverage wherever possible, using tools such as JasperGold or VC-Formal. - Develop and maintain machine-checked proofs for critical compiler transformations, ensuring correctness of lowering passes from our high-level programming model down to hardware - Build embeddings of our hardware description languages and simulator models into interactive theorem provers (e.g. Lean 4, Rocq, Isabelle/HOL), and use those embeddings to prove functional correctness and microarchitectural properties directly against the designs - Collaborate with architecture, compiler, and silicon verification teams to identify correctness properties worth proving and translate them into tractable proof obligations - Drive methodology for integrating formal tools (JasperGold, SymbiYosys, or equivalent) into our existing practices Who You Are - Hands-on experience with hardware model checking-writing SVA/PSL properties, running bounded or unbounded proofs, and closing out formal verification targets at block or subsystem level - Practical experience with at least one interactive theorem prover (Lean, Coq, Isabelle/HOL, Agda, or similar) - Experience embedding an existing

SOC Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next-generation AI-focused, server-class silicon. What You'll Do Here - Lead SoC architecture by translating Product Requirements Documents (PRDs) into SoC-level architectures in collaboration with subsystem architects and cross-functional teams - Define SoC architecture including memory, systems, interconnects, clocking, power, IP requirements, and system integration - Define system flows for power-up, boot, and recovery - Own PPA feasibility and drive power, performance, and area trade-offs with implementation teams - Own architectural specifications and documentation from definition through productization Who You Are - Industry experience in complex SoC architectures - Knowledge of memory systems and interconnect fabrics, including industry standards - Ability to define functional and PPA requirements from use cases - Sound architectural judgment in driving trade-off decisions - Excellent technical communication, documentation, and organizational skills - Experience collaborating across hardware, software, and third-party IP teams - Programming/scripting skills (verilog, bash, C/C++, python etc) - This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Compensation The US base salary for this full-time position is determined based

Runtime Engineer Mountain View, CA What MatX is Building MatX is building custom silicon for large-language-model inference and training, with HW/SW co-design across ISA, RTL, simulator, compiler, and kernels so each layer benefits from the others. The runtime owns the host-side stack and the contracts that bind those teams together. What You'll Do Here - Build the host-side interface library - device memory management, DMA, streams and events, sync primitives - that every compiler-emitted program runs on top of - Own and extend the executable format: the compiler→runtime contract, its versioning, the weight and quantization layouts that let compiler and runtime evolve independently - Design the custom-kernel ABI - calling convention, sync semantics, lifecycle - and the host-side marshaling layer (DLPack, the buffer protocol, numpy) that gets Python tensors to the device - Build Python bindings via PyO3, with a C-ABI shim as the alternative integration path for downstream consumers - Build the LLM inference serving stack - paged KV cache, continuous batching, request scheduling, token streaming - and the cluster orchestration primitives underneath it - Bring up interconnect topology from the host and own the failure-detection and clean-teardown path for stop-restructure-resume recovery across racks - Design what the chip exposes to host-side profilers and debuggers - perf counters, traces, and the Python surfaces ML engineers actually use - and hit measurable performance targets on runtime overhead and serving throughput Who You Are - Strong experience in a systems programming language - Rust, C, C++, or Go - including memory

Executive Operations Coordinator, Office of the CEO Mountain View, CA What MatX Is Building MatX is building cutting-edge AI infrastructure at the intersection of hardware and software, on a mission to make the world's best AI models run as efficiently as possible. We're growing fast, and our CEO's time is one of the most valuable resources in the company. This role exists to protect and multiply it. About This Role The Office of the CEO at MatX operates as a team of three: the CEO, his Chief of Staff, and you (reporting to the Chief of Staff). You'll own the operational surface area of this office, allowing the CoS and CEO to focus on company-wide strategy and operational decision-making. You'll turn calendaring, communications, and logistics into a multiplier for the CEO's impact on company outcomes. You'll learn how we work: how the CEO thinks and prioritizes, how the CoS works, and where the gaps are. You'll start filling those gaps on your own: drafting follow-up emails, figuring out next steps and who owns them during meetings, or proactively suggesting comms to address the themes you're hearing across the company. This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week, on Tuesday through Thursday What You'll Do Here - Calendar and time management. You own the CEO's schedule and use it to strategically spend his time. You'll learn company priorities, when he needs buffers, which "quick calls" are actually high-priority,

ASIC/SOC Silicon Physical Design Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII - Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) - Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout - Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL

SOC Intergration Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design. - Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL. - Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL. - Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL. - Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams. - Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements. - Provide technical support to package and board teams by defining SOC pin

Emulation Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. We're hiring a Senior/Staff Emulation Engineer to build the infrastructure, flows, and debug methodology behind our advanced connectivity SoCs. The role sits in the Emulation team, but the impact is broader: you'll create reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation. We're looking for a multi-disciplinary engineer with an out-of-the-box, can-do mindset - someone who sees a gap and builds the bridge, comfortable moving between RTL, software, tooling, system debug, and vendor flows. You don't need to be an expert in every area listed below. You do need a reuse-first mindset, strong software instincts, and the ability to learn quickly across boundaries. What You'll Do Here - Define and execute emulation strategy and test plans for complex connectivity SoCs. - Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu or Veloce. - Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and

Bluespec Design Engineer Mountain View, CA What MatX Is Building MatX is seeking engineers with strong Haskell skills to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon RTL at the full-chip or subsystem level. You will write hardware in Bluespec , a hardware description language rooted in Haskell's type system and semantics. If you've ever wished you could design hardware with the composability and correctness guarantees of a modern functional language, this is the role for you. You do not need prior hardware experience to apply - if you know Haskell, we will teach you the hardware side. What You'll Do Here - Build production hardware for compute, memory management, and high-speed connectivity - Develop reusable, parameterized Bluespec libraries that scale across the chip - Shape hardware architecture by leveraging the power of Bluespec to explore implementation tradeoffs and converge on the best designs - Create innovative tooling for our hardware/software ecosystem to help us build correct, high-performance hardware faster Who You Are - Proficient in Haskell - you're comfortable with monads, typeclasses, higher-order functions, and do-notation. You understand why return injects a value into a monadic context and what <- does in a do-block - Strongly willing to quickly ramp on Bluespec Haskell (BH) - Strong engineering fundamentals - you write clean, well-tested, well-documented code and are comfortable with build systems, version control, and CI workflows Bonus Points If You Have

Silicon Micro-Architect and RTL Designer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design - Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design - Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout - Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results Who You Are - Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon - 2 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows - Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed

AI Accelerator Silicon Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. MatX is seeking an AI Accelerator Compute Architect to help define the compute architecture for our next-generation GenAI accelerators. What You'll Do - Define the architecture for MatX's AI compute subsystem, including ISA, connectivity, memories, and control.. - Derive architectural requirements from AI use cases. - Conduct analytical and empirical performance analysis. - Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA. - Work through power, area, performance tradeoffs with stakeholders. - Support test plan reviews, first-silicon bring-up, and post-silicon debug. Who You Are - Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures. - Experience translating workloads into hardware architecture. - Solid microarchitecture fundamentals. - First-principles understanding of latency, throughput, utilization, and scalability. - Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs. - Programming, code optimization, or kernel-level performance analysis experience. -

Build Systems Engineer (Bazel) Mountain View, CA What MatX Is Building MatX builds custom AI accelerator silicon. The build system is the backbone: it wires together RTL, a stack of commercial EDA tools (simulation, synthesis, place-and-route, lint/CDC), and a Rust/Python software stack into one hermetic, reproducible pipeline. We run on Bazel with bzlmod, RBE, custom rules, and a small but tight set of platform-level abstractions. You'll join a small group that owns the build graph, the toolchains, the rules that wrap each EDA tool, and the CI infrastructure that keeps thousands of targets green. What You'll Do Here - New EDA tool integrations. Wrap a closed-source tool in a hermetic Bazel rule with proper providers, runfiles, and execution constraints. Add a new front-end stage to an existing toolchain; add a rule for test variants that share configuration; wire a third-party generator into our verilog graph as a first-class dep - Bazel version migrations. Lead upgrades (8.x → 9.x) and the bzlmod/ MODULE.bazel housekeeping that comes with them - Hermeticity work. Hunt down the implicit assumptions: system Python, system gcc, leaked /usr/bin deps, host-state in tests. Replace them with hermetic toolchains and tracked inputs - Refactors that delete code. Rewrite a fragmented family of test macros in terms of one shared rule. Remove a homegrown wrapper rule once upstream covers the case. Extract a common aspect helper used by three places that duplicated it. The good PRs net negative - Build performance. Persistent workers for slow tools, RBE configs, action graph

Rust SW-Silicon Co-verification Engineer Mountain View, CA What MatX Is Building MatX is seeking engineers with strong Rust skills to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. You will write Rust tests that verify our software models and hardware design behave identically and match the specification. Your tests and tooling will exercise the chip's software model and hardware design side by side, catching mismatches before they become silicon bugs. If you've ever wished your knack for writing correct, thorough Rust could be applied to something where correctness has million-dollar consequences, this is the role for you. You do not need prior hardware or verification experience to apply - if you know Rust, we will teach you the hardware side. What You'll Do Here - Write Rust tests that verify our software models and hardware design agree with each other and with the specification - Build test infrastructure in Rust that makes it easy to add new tests and run them at scale - Develop and maintain harnesses that connect your tests to our hardware - Write tests that systematically explore corner cases and rare event sequences - both targeted tests and tests that use randomization to find surprises - Work with architects and design engineers to turn specifications into concrete, testable properties Who You Are - Proficient in production Rust - you've shipped real systems. You're comfortable with ownership, traits, generics with bounds, and enums as sum types. You understand why Result is better