Rambus INC jobs

SPE Applications/Validation Engineering San Jose, CA, US; Johns Creek, GA, US Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr Principal Applications Engineer with DRAM and failure analysis expertise to analyze and debug complex technical issues involving DRAM, memory interface chips, DIMM, server and BIOS operation and interaction. This individual will support international customers of Rambus DDR4 and DDR5 memory interface chips in South Korea and Asia. You will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Analyze and debug complex technical issues involving server memory and manage customer issues to a satisfactory conclusion. Support technical qualification of new chip designs to secure customer design wins. Assist with validation and debug of new memory interface chips for DDR5 servers. Collect and analyze signal integrity data at the system level. Conduct failure analysis and prepare failure analysis and 8D reports. Gather customer technical feedback and communicate to Marketing and Engineering teams. Present technical updates to customers and company management in writing and verbally via quality presentations. Prepare technical documentation such as datasheets, user guides and application notes. Qualifications Familiar with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers.

Senior Design Verification Engineer - PCI-Express Controller IP SOFIA, UNAVAILABLE, BG Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional mid tosenior-level individual contributor Design Verification Engineer to join our PCIe Express IP Products team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL Verification activities related to PCIe Controller SoftIP development, on leading-edge PCI-Express and CXL controller technologies. This is a Full Time position, reporting to the local onsite Verification management. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work. Responsibilities Duties in this position will include: Testbench and test sequence development for verification of new controller technologies and features Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design Development & support of Verification environment scripting and capabilities Qualifications Bachelors Degree or above in EE/CS, at least 5-7 years prior experience with HDL logic Design-Verification SystemVerilog and/or UVM testbench, Verilog/SystemVerilog logic design, /RTL familiarity/project work Pre-existing Experience / familiarity with one or more I/O controller technologies such as PCI-Express, is highly desireable Working experience with Python and TCL scripting languages preferred About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP

SMTS Reliability Engineering Chupei City, UNAVAILABLE, TW Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Reliability Engineer to join our Reliability Engineering team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Sr Reliability Engineer, the candidate will be reporting to the Director of Reliability Engineering and is a Full-Time position. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Own Ongoing Reliability Monitoring for production, task covers from ORM plan, coordinating test, data analysis, to final ORM report. Drive failure analysis to root causes and implementation of corrective actions by interacting with cross-function teams, design, validation, packaging, PE/TE, etc. Collaborate with foundries and package houses (OSATs) to assess, characterize, and improve product quality and reliability Reviewing and understanding reliability test results and making appropriate engineering judgement and decisions based on data, and driving appropriate action, Qualifications S/M.S in Electrical Engineering, Physics, Material Science, or equivalent experience. Experience in any one of the following semiconductor IC relevant fields, Quality, Reliability, Process, Validation, PE/TE etc. familiar with JEDEC qualification standards is a plus. Excellent interpersonal communication and writing skills while interacting with suppliers, customers, and internal staff. Ability to independently learn and collaborate for problem-solving.

Digital Design Engineer - New College Grad San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional MTS Digital Design Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Work with analog/digital design team for new product development Responsible for RTL coding, functional simulation, analog-block Verilog model, post-pr simulation Support bench test, support ATE test Support chip bringing-up, debugging, failure analysis, characterizations and product release efforts Qualifications Master degree or above in EE or related field Experience in the area listed below: Embedded SRAM/OTP/Efuse/MTP controller Design for test for digital block, analog block Communication bus such as I2C/I3C/SPI/AHB/APB Familiar to schematic editor Being Familiar to mixed signal design and backend is a plus Mass product experience is a plus Self-motivated and proactive Good communication skills and a strong team player About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider

Lead MTS Physical Design/STA Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip's for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 10 - 12 years of experience, out of which

Director/Sr Manager - Silicon IP Sales San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Director, Sales to join our Sales team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a Director, Sales, you'll play a pivotal role in (add brief overview of key responsibilities and impact). In this full-time role, you'll report directly to our Sr Director, Sales. The focus of this Sales role is to develop and grow our Interface IP and Security business, with focus on strategic customer relationships and opportunities. Main responsibility is to achieve assigned sales targets by developing and maintaining customer accounts. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote wor Responsibilities Develop and execute business growth plans for key strategic accounts Accountable to deliver Revenue, Gross Margin, and Design Win Revenue goals Forecasting long-term demand and near-term revenue Responsible for assessing current opportunities, resources, and capabilities needed to meet or exceed sales plan Responsible for developing and executing innovative sales approaches to drive revenue and profitability growth Maintain and grow the existing customer base while increasing Rambus' focus on pursuing and investing in new high-value accounts Work with

SPE Signal Integrity Engineer Johns Creek, GA, US; San Jose, CA, US; San Jose, UNAVAILABLE, US; Bangalore, UNAVAILABLE, IN; UNAVAILABLE, UNAVAILABLE, Seoul Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU's engineering team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed

Lead Physical Design Engineer Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Physical Design Engineer to join our MIC team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification, Take complete ownership for implementation of both Top/Block level designs. Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 28nm nodes or below. Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM, Timing Closure, constraint (sdc) development) Well versed with the block and chip level timing closure (STA) and timing closure methodologies. Also need to have experience with constraints development. Experience in Hierarchical and Flat timing flow bring-up and timing analysis on interface paths. Block level/Fullchip/SOC level/Mixed signal timing path analysis and fixing. Must have knowledge of low power design. (cpf, upf CLP). Should be able to provide clear directions to the team on various implementation and signoff flows Should be well versed in LEC flow and debugging issues independently. Role involves tasks in estimating power using industry standard tool

Mgr Product Engineering Taipei, UNAVAILABLE, JP; Taipei, UNAVAILABLE, JP Overview Mgr Product Engineering (based in Korea or Taiwan) will join a dynamic and multi-disciplinary team which will ensure product reliability and gross margins meet expectations for products in our memory and interface division. This engineer will be responsible for day-to-day product engineering activities by collaborating within a cross-functional team including test engineers, OSATs and fabs. Candidates for this level position must be capable of working independently, defining technical direction, be self-motivated and a collaborative team player Responsibilities Bring-up and debug first silicon quickly to identify any potential design, process or testing issues. · Ramp up yield for new product introduction. · Perform yield analysis to ensure products yield to D0 projections. · Identify the low yield detractors and the root cause. · Work with Taiwan/Korean subcontractors to ensure smooth production, for both Wafer Sort and Final Test, on the day-to-day basis: tester correlation, hold lot disposition etc. · Generate real time SBL and SYL for all products to identify production outliers. · Generate customer reports per commitment. · Identify areas of improvement in current productions. · Drive test time reduction to product COG metric or below. · Help to manage WIP & cycle time and provide constructive feedback to improve. Qualifications BSEE required, MSEE preferred. · 15+ of experience with product/test engineering. · Programming skills preferred (C++, Java script or Python experience). · Wafer Sorting (WS) and FT NPI setup/production experience preferred. · Strong test data analysis capability. (Synopsis, Galaxy,

Senior RAM Engineer Australia-Springfield Central | Australia-Fortitude Valley

Lead MTS Program Management Rotterdam, UNAVAILABLE, NL; Vught, UNAVAILABLE, NL; Montreal, UNAVAILABLE, CA Overview We are seeking an experienced Program Manager with a strong technical foundation and a proven track record of delivering complex, multi‑disciplinary programs. In this role, you will lead cross‑functional initiatives, manage program roadmaps, and ensure successful execution from concept to completion. You will work closely with engineering, product management, and cross‑region stakeholders to drive alignment, remove roadblocks, and keep programs running smoothly. This role is based in either our Montreal office or our Netherlands locations. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Lead and manage end‑to‑end program execution across multiple engineering teams. Develop and maintain program plans, schedules, milestones, and metrics. Proactively identify risks, dependencies, and resource gaps, and drive mitigation plans. Facilitate effective communication across engineering, product, quality, and operations teams. Drive cross‑functional alignment on requirements, scope, timelines, and deliverables. Report program status, progress, and risks to leadership and key stakeholders. Continuously improve program management processes and operational efficiency. Qualifications 5 to 10 years of experience as a Program Manager in a technical environment. Engineering degree (Electrical, Computer, Mechanical, Software, or related). Demonstrated experience managing complex technical programs with multiple stakeholders. Strong communication, leadership, and problem‑solving skills. Ability to work effectively across global teams and time zones. Preferred Qualifications (Nice to Have) Experience in the

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