Mgr Product Engineering

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$102,662 U.S. median for this role

Projected growth (BLS Employment Projections)

+5.4% - Faster than average

Matched to SOC 11-1021 - Product Management aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company Verified - from the job posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Mgr Product Engineering Taipei, UNAVAILABLE, JP; Taipei, UNAVAILABLE, JP Overview Mgr Product Engineering (based in Korea or Taiwan) will join a dynamic and multi-disciplinary team which will ensure product reliability and gross margins meet expectations for products in our memory and interface division. This engineer will be responsible for day-to-day product engineering activities by collaborating within a cross-functional team including test engineers, OSATs and fabs. Candidates for this level position must be capable of working independently, defining technical direction, be self-motivated and a collaborative team player Responsibilities Bring-up and debug first silicon quickly to identify any potential design, process or testing issues. · Ramp up yield for new product introduction. · Perform yield analysis to ensure products yield to D0 projections. · Identify the low yield detractors and the root cause. · Work with Taiwan/Korean subcontractors to ensure smooth production, for both Wafer Sort and Final Test, on the day-to-day basis: tester correlation, hold lot disposition etc. · Generate real time SBL and SYL for all products to identify production outliers. · Generate customer reports per commitment. · Identify areas of improvement in current productions. · Drive test time reduction to product COG metric or below. · Help to manage WIP & cycle time and provide constructive feedback to improve. Qualifications BSEE required, MSEE preferred. · 15+ of experience with product/test engineering. · Programming skills preferred (C++, Java script or Python experience). · Wafer Sorting (WS) and FT NPI setup/production experience preferred. · Strong test data analysis capability. (Synopsis, Galaxy,

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