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Senior Technical Lead - Signal / Power Integrity Engineer (Onsite)

Cisco - San Jose, California, US

Posted May 21, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked Jun 13, 2026
Salary
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401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work
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Application

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Deadline
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Where they hire

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About this role

Senior Technical Lead - Signal / Power Integrity Engineer (Onsite) San Jose, California, US The application window is expected to close on: 05/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close 2/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is an onsite role based in the San Jose, CA office. While the team may have hybrid days, this is at the discretion of the team and is subject to change at any time. Meet the Team The Cisco Service Provider SI team is seeking a Senior Technical Lead, Signal/Power Integrity Engineer for the design and analysis of high-speed interconnects and power distribution networks. As a member of the Service Provider SI team, you will help develop the next generations of Cisco Switch and Router products, participating in the definition and design of current and next-generation ASICs, packages, printed circuit boards (PCBs), and system interconnects. You will be working in a larger team, collaborating closely with system architects, ASIC engineers, package engineers, and versatile and knowledgeable SI/PI engineers in the creation of next-generation networking products. Your Impact High-speed link modeling and simulation, including high-speed I/O, IC package, and system interconnections. Modeling and analyzing power delivery networks. Electromagnetic modeling of complex 3-dimensional structures. Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs.

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Apply link verified; last checked Jun 13, 2026.

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