Senior Technical Lead, Signal/Power Integrity Hardware Engineer (Onsite)

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$191K-$281K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

103% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Work mode

Onsite From the posting source checked Jun 20, 2026

In-office days

5 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Jun 26, 2026 From the posting source checked Jun 20, 2026

Where they hire

State eligibility is not yet verified.

About this role

Senior Technical Lead, Signal/Power Integrity Hardware Engineer (Onsite) San Jose, California, US The application window is expected to close on: 06/26/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you commute to our San Jose, CA office 5 days per week. Meet the Team The Cisco Service Provider SI team is seeking a Senior Technical Lead, Signal/Power Integrity Engineer for the design and analysis of high-speed interconnects and power distribution networks. As a member of the Service Provider SI team, you will help develop the next generations of Cisco Switch and Router products, participating in the definition and design of current and next-generation ASICs, packages, printed circuit boards (PCBs), and system interconnects. You will be working in a larger team, collaborating closely with system architects, ASIC engineers, package engineers, and versatile and knowledgeable SI/PI engineers in the creation of next-generation networking products. Your Impact High-speed link modeling and simulation, including high-speed I/O, IC package, and system interconnections. Modeling and analyzing power delivery networks. Electromagnetic modeling of complex 3-dimensional structures. Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs. Write signal integrity design guidelines, test plans, and test reports. Decide appropriate PCB material, stack-up, and work with vendors to address any DFM (Design for Manufacturability) issues. Support prototype function bring-up, validation, and troubleshooting. Work closely with other hardware function teams including HW design, eCAD, Mechanical, Power, EMC, and Diagnostics

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.