ASIC Engineering Technical Leader

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$184K-$264K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

92% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Onsite From the posting source checked Jun 20, 2026

In-office days

5 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineering Technical Leader San Jose, California, US The application window is expected to close on: 05/07/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon. Influence system architecture and key design decisions across complex SoC subsystems. Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation. Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon. Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges. Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team. Lead debug and root-cause analysis across simulation,

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.