ASIC Engineering Technical Leader

Benefits

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Family-building benefits

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Verification

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Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Application

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About this role

ASIC Engineering Technical Leader San Jose, California, US The application window is expected to close on: 05/07/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role requires being onsite in San Jose, CA at least 4 days/week Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon. Influence system architecture and key design decisions across complex SoC subsystems. Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation. Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon. Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges. Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team. Lead debug and root-cause analysis across simulation,

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