Ingram Micro jobs

Optical technician Parvomay, BULGARIA, Bulgaria Company Description: It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly 30 years later, that question still fuels everything we do at Intuitive . As a global leader in robotic-assisted surgery and minimally invasive care , our technologies-like the da Vinci surgical system and Ion -have transformed how care is delivered for millions of patients worldwide. We're a team of engineers, clinicians, and innovators united by one purpose: to make surgery smarter, safer, and more human. Every day, our work helps care teams perform with greater precision and patients recover faster, improving outcomes around the world. The problems we solve demand creativity, rigor, and collaboration. The work is challenging, but deeply meaningful- because every improvement we make has the potential to change a life. If you're ready to contribute to something bigger than yourself and help transform the future of healthcare , you'll find your purpose here. Job Description: Primary Function of Position: Production of small optical elements and assemblies of the highest standard and quality. He works closely with the other team members, the division and department manager to achieve the goals in the areas of quantities, efficiency, accurate time documentation and scrap. In each of these areas, the overall performance of the team is measured against these targets for each quarter. Roles and Responsibilities: Independent processing of small micro-optical parts and assemblies according to company-specific specifications Independent assessment of the work results by measuring

Physical Designer Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and drive the implementation of physical design methodologies. Take ownership of one or more physical design partitions or top level. Drive to the closure of timing and power consumption of

Senior Silicon Physical Design Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements. Collaborate with cross-functional teams to debug failures or performance shortfalls and

Manager, FP&A Shanghai, Shanghai, China Company Description: About AbbVie AbbVie's mission is to discover and deliver innovative medicines and solutions that solve serious health issues today and address the medical challenges of tomorrow. We strive to have a remarkable impact on people's lives across several key therapeutic areas including immunology, oncology and neuroscience - and products and services in our Allergan Aesthetics portfolio. For more information about AbbVie, please visit us at www.abbvie.com . Follow @abbvie on LinkedIn, Facebook , Instagram , X and YouTube. Job Description: KEY DUTIES AND RESPONSIBILITIES: Describe scope: % of Time or Importance Support strategy goal setting and Strategic financial objectives. 15% Drive business planning process and roll out Financial plans. Assure the quality and strategy alignment of China expansion and growth strategy plan, budget and forecasts. Coordinate with Intl./Global to ensure timely and high quality China consoled reporting deliverables. 25% Navigate, provide the financial guidance to Business Unit General Managers, and Marketing Directors to manage Performance and objectives of business plans. Propose intervention, early warning and risk control. 25% Analysis and decision support. Offer analytical support for decisions on new product/new business/ new channel, micro resource allocation, organization expansion/organization optimization, sample, and key contracts negotiation. 20% ROI assessment for strategic initiatives. 15% Qualifications: Bachelor's degree on Finance or Economics related subject. Minimum 8+ years track record in Finance field of Multinational companies, at least 4+ years in FP&A position prior to Allergan Healthcare or FMCG industry preferred. CPA, ACCA or CMA, MBA in equivalent

Senior Manager, FP&A Shanghai, Shanghai, China Company Description: About AbbVie At Allergan Aesthetics, an AbbVie company, we develop, manufacture, and market a portfolio of leading aesthetics brands and products. Our aesthetics portfolio includes facial injectables, body contouring, plastics, skin care, and more. Our goal is to consistently provide our customers with innovation, education, exceptional service, and a commitment to excellence, all with a personal touch. For more information, visit https://global.allerganaesthetics.com/. Follow Allergan Aesthetics on LinkedIn. Job Description: KEY DUTIES AND RESPONSIBILITIES: Describe scope: % of Time or Importance Support strategy goal setting and Strategic financial objectives. 15% Drive business planning process and roll out Financial plans. Assure the quality and strategy alignment of China expansion and growth strategy plan, budget and forecasts. 20% Navigate, provide the financial guidance to Business Heads, and Marketing Director to manage performance and objectives of business plans. Propose intervention, early warning, and risk control. 25% Analysis and decision support. Offer analytical support for decisions on new product/new business/ new channel, commercial policy, micro resource allocation, organization expansion, sample, and key contracts negotiation. 10% Product value chain management. Lead pricing strategy for both existing and new launch products, commercial policy framework, G2N process enhancement. Regularly update pricing structures in line with budget/forecast expectation. Ensure closely monitoring of price change and commercial policy implementation and identify gaps (if any) with mitigation plan. 10% Market intelligence preparation by analyzing market segmentations, strategic expansions, competitive dynamics analysis to help overall company strategy setting and execution tracking. 10% Lead and

Senior Silicon Architect Mountain View, CA, USA The US base salary range for this full-time position is $218,000 - $237,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google . Position reports to the Google Mountain View, CA office & may allow for a hybrid schedule as per Google policy. Artificial intelligence will be one of humanity's most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority. We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort. Lead the definition of chip IP architectures, memory hierarchy, interconnect fabrics, and IP integration to meet product requirements. Utilize high-level performance and power models to guide architectural decisions and conduct detailed trade-off analyses to optimize for system-level goals. Create and maintain detailed architectural specification documents that guide micro-architecture and design teams throughout the project lifecycle. Collaborate with software, product management, and physical design teams to ensure the hardware architecture is feasible, aligns with software needs, and meets all product requirements. Drive the

Senior Physical Design Floorplan Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and drive to the

Customer Service Analyst - Spanish required (evening shift) BUCHAREST, Romania, RO As a member of the Support organization, your focus is to deliver post-sales support and solutions to the Oracle customer base while serving as an advocate for customer needs. This involves resolving post-sales non-technical customer inquiries via phone and electronic means, as well as, technical questions regarding the use of and troubleshooting for our Electronic Support Services. A primary point of contact for customers, you are responsible for facilitating customer relationships with Support and providing advice and assistance to internal Oracle employees on diverse customer situations and escalated issues. - 3-5 Years experience in hospitality industry or technical support - Database knowledge - Internet troubleshooting skills - Knowledge of operating systems - Excellent communicator with strong time management and prioritisation skills - Ability to work under pressure and multi-task - Strong analytical skills - Availability to work in shifts and during weekends - Previous experience of Micros Products would be advantageous - Multilingual proficiency is mandatory to support our diverse global customer base - Strong customer service skills As a member of the Support organization, your focus is to deliver post-sales support and solutions to the Oracle customer base while serving as an advocate for customer needs. This involves resolving post-sales non-technical customer inquiries via phone and electronic means, as well as, technical questions regarding the use of and troubleshooting for our Electronic Support Services. A primary point of contact for customers, you are responsible for facilitating customer relationships

Physical Design Engineer Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Physical Design Engineer, you will collaborate closely with cross-functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro-architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power, and Area (PPA) for the next generation of Tensor Processing Unit (TPU) blocks and sub-chips. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping

Senior Software Engineer, Google Cloud Storage New York, NY, USA Google Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. In this role, you will drive the future of flash storage at Google. You will work on projects, designing and implementing advanced scheduling algorithms for improved user isolation and QoS, micro-optimizing server code for ultra-low latency. You will be responsible for enhancing data integrity through advanced error detection, collaborating with platform teams on design and qualification of new solid-state drive (SSD) hardware, and developing innovative technologies like SmartFTL and write amplification (WAF) reduction techniques. Google Cloud accelerates every organization's ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google's cutting-edge technology, and

Senior AI Developer / Architect - SAP Labs East Asia Singapore Senior AI Developer / Architect - SAP Labs East Asia Singapore | Country Singapore | Internal Posting Location Singapore We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. *SAP will be prioritizing candidates with full working rights in Singapore* What you'll do Your tasks include: Design and build production-grade conversational services - Joule and micro-services in Java and Python. Explore, understand, and implement most recent technologies and approaches for cloud platform and data pipelines. Design and define ADR, ACD for the solution on new features or integrations. Drive engineering across Architecture, Implementation, Testing, and Delivery of the Product. Producing high-quality, maintainable code with an emphasis on modularity, testing, and performance Build strong interpersonal relationships with internal and external stakeholders Mentoring junior engineers, performing code reviews, and contributing to a high-performance team culture. Solving complex integration and performance challenges across systems, often working across time zones in a global team set Right attitude: Team first attitude. Ensure

Senior Data Scientist, Search Growth Mountain View, CA, USA; +1 more Search has entered a new era. On the one hand, user's needs have gone beyond info-seeking to problem-solving. On the other hand, Search faces severe competition from 3p apps. Growth is a top line goal for Search in this new era. The central Search growth data science team drives Search growth through data-driven growth strategies. We solve complex growth problems both at macro-level and micro-level, through growth measurement methodology development, growth data product development, and growth related analysis and insights. This is a high profile role with executive level visibility. In this role, you will get to work on all aspects of data science, from data science methodology to tooling, both at macro strategy level and at daily product development level. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $174000 - $253000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Search growth measurement methodology development (e.g., Empirical Bayes to conquer high uncertainty in live experiments, growth surrogates to connect short term live experiment signals with long-term growth). Launch based growth analysis and insights, understand different growth levers and their contributions to growth, and provide actionable insights on areas of investment. Work with 3p data to understand the competitive landscape, reason through its strategic implications, and make data-driven strategic action recommendations. Work with the Search growth engineering team to develop growth data

Senior CPU Design Verification Engineer, Emulation Austin, TX, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis. Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches. Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation. Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers. Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in both Design

MicroLED Display Reliability Engineer, Augmented Reality, Raxium Fremont, CA, USA As a MicroLED Display Reliability Engineer, you will own the direction and execution of reliability initiatives across the product lifecycle. You will drive transformational improvements in reliability for microLED based display products, covering multiple form factors - including on-chip (for Gallium Nitride (GaN)-on-Silicon based micro-LED emitter planes) and on-display. You will shape long-term strategy, and influence executive stakeholders both internally and externally. You will require technical expertise in optoelectronics reliability, cross-functional leadership, and the ability to operate in a dynamic environment. You will collaborate extensively with cross-functional partners in development (e.g., LED, Display Panel), Process Engineering, Manufacturing and Operations to embed design for reliability into the display panel lifecycle.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop and implement reliability programs for various device and display product reliability tests including operational lifetests, device aging, environmental stresses and reliability

MicroLED Display Reliability Engineer, Augmented Reality, Raxium Fremont, CA, USA As a MicroLED Display Reliability Engineer, you will own the direction and execution of reliability initiatives across the product lifecycle. You will drive transformational improvements in reliability for microLED based display products, covering multiple form factors - including on-chip (for Gallium Nitride (GaN)-on-Silicon based micro-LED emitter planes) and on-display. You will shape long-term strategy, and influence executive stakeholders both internally and externally. You will require technical expertise in optoelectronics reliability, cross-functional leadership, and the ability to operate in a dynamic environment. You will collaborate extensively with cross-functional partners in development (e.g., LED, Display Panel), Process Engineering, Manufacturing and Operations to embed design for reliability into the display panel lifecycle.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop and implement reliability programs for various device and display product reliability tests including operational lifetests, device aging, environmental stresses and reliability

CPU Performance Architect, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more As a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google's advanced SoC products. You will collaborate cross-functionally with android applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM's) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture, or equivalent practical experience. 4 years of experience in microprocessor

ASIC RTL Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical

Senior UX Designer, Search Design System Mountain View, CA, USA; +1 more At Google, we "Focus on the user and all else will follow." Our Interaction Designers transform complex tasks into intuitive, easy-to-use experiences for billions of people. From creating user flows and wireframes to building mockups and prototypes, you will envision and bring product experiences to life with an inspired, refined, and magical feel. You will join our multi-disciplinary UX team, collaborating with Engineering and Product Management, leveraging user insights to create industry-leading products. As an Interaction Designer, you'll apply user-centered design methods to craft industry-leading user experiences from concept to execution, working with design partners to evolve the Google design language to build beautiful, innovative products. As a Senior UX Designer on the Search Design System team, you will serve as a design architect, balancing systemic structural thinking with a high-craft execution of fluid, native interactions. In this role, you will shape the living, cross-platform foundations that power the future of Search, infusing fluidity, delight, and a native-first mindset into a mature design system. You will seamlessly shift between defining macro-level component architectures and crafting micro-level interactive details. You will use high-fidelity prototyping and dynamic specifications to move the system beyond static layouts into adaptive, intelligent logic for both human teams and AI workflows. Beyond architecting tokens and components, you will act as a critical bridge to engineering and a cultural catalyst-converting native design best practices and up-skilling feature teams across the broader organization. In Google Search, we're

Senior ASIC RTL Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in

Tech Lead, SoC Design Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead a team of RTL Design engineers performing tasks related to IP development and/or SOC Design. Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.). Participate with architecture and system design teams in architecture definition, die area estimation, power optimization, and performance enhancements. Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. Define microarchitecture for a subsystem/SoC top-level. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related

Tech Lead, SoC Design Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead a team of RTL Design engineers performing tasks related to IP development and/or SOC Design. Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.). Participate with architecture and system design teams in architecture definition, die area estimation, power optimization, and performance enhancements. Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. Define microarchitecture for a subsystem/SoC top-level. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related

Senior CPU Performance Architect Mountain View, CA, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan and evaluate ARM's architecture features from both architecture and performance aspects. Develop a performance model for performance analysis and microarchitecture studies. Lead collaboration with design and verification teams to develop efficient CPU implementation. Define and write CPU subsystem architecture specifications. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer

ASIC RTL Design Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/ Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer

CPU Architecture and Performance Architect New Taipei, Banqiao District, New Taipei City, Taiwan Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a CPU architecture and performance architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google's advanced SoC products. You'll have the opportunity to collaborate with talents in system performance and software teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases. Leveraging your CPU-specific knowledge and leadership, you'll be guiding junior CPU architects and working with engineers in power, thermal, security, and physical design teams to determine the CPU subsystem configuration and features. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development, pre-silicon performance correlation, and post-silicon performance analysis and debugging. Plan and evaluate CPU architecture features from both architecture and performance angles. Develop a performance model for