ASIC RTL Design Engineer III, Silicon

Benefits

Parental leave

18 weeks Source: https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/. source Last checked May 7, 2026.

Non-birth-parent leave

18 weeks Source: https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/. source Last checked May 7, 2026.

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC RTL Design Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/ Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.