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CPU RTL Design

Compx International INC - Cupertino, CA, United States

Posted Jun 10, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
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Salary
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401(k) match
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Market context

U.S. role benchmark (BLS OEWS)
$66,396 U.S. median for this role
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Design From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
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Weekend work
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Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

CPU RTL Design Cupertino, CA, United States Company Description: Positions are open for full-time in the areas of CPU and SOC architecture development. We are looking for all levels of talent, from the entrance to advanced levels of experience. Job Description: RTL ownership - development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Validation - support test bench development and simulation for functional and performance verification Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance Qualifications: BS or MS in Computer or Electrical Engineering with 5+ years of CPU RTL experience A thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling, and register renaming, out-of-order execution, integer, and floating point execution, load/store execution, cache, and memory subsystems Knowledge of Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using an interpretive language such as Perl or Python Additional Information: All your information will be kept confidential according to EEO guidelines.

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