Programmable Logic Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$156K-$246K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

72% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Programmable Logic Design Engineer Germantown, Maryland; Carlsbad, California; Independence, Ohio; Englewood, Colorado About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration. The day-to-day Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications Develop testbenches and help maintain and update system level verification environment Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs Develop timing constraints, analyze timing results, and implement design changes required to close timing Generate and collaborate on required design documents, development requirements, specifications and verification protocols Responsible for owning and driving technical issues to resolution Integrate and debugs design in the laboratory What you'll need Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field 5-8 years FPGA design experience, including Xilinx Vivado Strong knowledge of System Verilog Experience with RTL design for various signal processing blocks, including but

Read the full description at careers-viasat.icims.com. FewerJobs shows a preview and links to the original posting.