Employer profile
Compx International INC
3 open roles indexed with location, benefit, and apply-link signals where available.
Open roles
Showing the most recent indexed roles for this employer.
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CPU Performance Modeling
Cupertino, CA, United States
unspecified Salary not disclosedCPU Performance Modeling Cupertino, CA, United States Company Description: Positions are open for full-time in the areas of CPU and SOC architecture development. We are looking for all levels of talent, from the entrance to advanced levels of experience. Job Description: The successful candidate will take a leadership position in a semi-custom performance modeling team to develop pre-silicon performance models for next generation CPUs This role will involve developing new performance models, evaluating architectural features, and supporting pre-silicon performance projections for CPU Communication skills, both written and oral, as well as organization skills are essential for this role You will approach sophisticated problems with a firm methodology and problem-solving technique and conduct experiments and analysis to formulate recommendations and next steps for other colleagues and SOC and IP design teams You will formally present your findings to co-workers, teams, and customer engineering teams Develop cycle-accurate and abstract performance models Carry out investigations to evaluate new microarchitectural features and algorithms Correlate models against RTL and post-silicon results Proficient at SW programming with good understanding of C++, C, and Python Qualifications: Bachelor/Masters/Ph.D. degree in Electronics/Computer Engineering or Computer Science with emphasis on computer architecture Additional Information: All your information will be kept confidential according to EEO guidelines.
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CPU Design Verification
Cupertino, CA, United States
unspecified Salary not disclosedCPU Design Verification Cupertino, CA, United States Company Description: Positions are open for full-time in the areas of CPU and SOC architecture development. We are looking for all levels of talent, from the entrance to advanced levels of experience. Job Description: Work closely with architecture and RTL designers on verifying the functionality correctness of the design Develop test plans and test environments Develop tests in assembly, C, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers or C-base transactor to verify the design Qualifications: The ideal candidate should have 5+ years of CPU verification experience In-depth knowledge of digital logic design, chip architecture, and microarchitecture Experience with expertise in developing testplans/testbenches, C-based transactors, and writing/debugging assembly-based tests Experience with advanced verification techniques such as formal and assertions a plus Experience in silicon bring up a plus Should be a team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design Additional Information: All your information will be kept confidential according to EEO guidelines.
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CPU RTL Design
Cupertino, CA, United States
unspecified Salary not disclosedCPU RTL Design Cupertino, CA, United States Company Description: Positions are open for full-time in the areas of CPU and SOC architecture development. We are looking for all levels of talent, from the entrance to advanced levels of experience. Job Description: RTL ownership - development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Validation - support test bench development and simulation for functional and performance verification Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance Qualifications: BS or MS in Computer or Electrical Engineering with 5+ years of CPU RTL experience A thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling, and register renaming, out-of-order execution, integer, and floating point execution, load/store execution, cache, and memory subsystems Knowledge of Verilog and/or VHDL Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using an interpretive language such as Perl or Python Additional Information: All your information will be kept confidential according to EEO guidelines.