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CPU Design Verification

Compx International INC - Cupertino, CA, United States

Posted Jun 10, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
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Salary
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401(k) match
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Market context

U.S. role benchmark (BLS OEWS)
$66,396 U.S. median for this role
Projected growth (BLS Employment Projections)
+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Design From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
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Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

CPU Design Verification Cupertino, CA, United States Company Description: Positions are open for full-time in the areas of CPU and SOC architecture development. We are looking for all levels of talent, from the entrance to advanced levels of experience. Job Description: Work closely with architecture and RTL designers on verifying the functionality correctness of the design Develop test plans and test environments Develop tests in assembly, C, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers or C-base transactor to verify the design Qualifications: The ideal candidate should have 5+ years of CPU verification experience In-depth knowledge of digital logic design, chip architecture, and microarchitecture Experience with expertise in developing testplans/testbenches, C-based transactors, and writing/debugging assembly-based tests Experience with advanced verification techniques such as formal and assertions a plus Experience in silicon bring up a plus Should be a team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design Additional Information: All your information will be kept confidential according to EEO guidelines.

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