ASIC Design Verification Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$152K-$219K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

59% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Jun 1, 2026 From the posting source checked Jun 20, 2026

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Engineer San Jose, California, US The application window is expected to close on: 06/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco's core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One (#CiscoSiliconOne) -the industry's only unified silicon architecture spanning top-of-rack switches to web-scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio . Come join us and take part in shaping Cisco's groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco's hardware platforms. You will: Participate in the ASIC design verification for Cisco high-end switching products. Perform end-to-end verification of design blocks and top-level Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis. Construct testbenches components like scoreboard, agents, sequencers,

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.