CPU Performance Modeling

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

CPU Performance Modeling Cupertino, CA, United States Company Description: Positions are open for full-time in the areas of CPU and SOC architecture development. We are looking for all levels of talent, from the entrance to advanced levels of experience. Job Description: The successful candidate will take a leadership position in a semi-custom performance modeling team to develop pre-silicon performance models for next generation CPUs This role will involve developing new performance models, evaluating architectural features, and supporting pre-silicon performance projections for CPU Communication skills, both written and oral, as well as organization skills are essential for this role You will approach sophisticated problems with a firm methodology and problem-solving technique and conduct experiments and analysis to formulate recommendations and next steps for other colleagues and SOC and IP design teams You will formally present your findings to co-workers, teams, and customer engineering teams Develop cycle-accurate and abstract performance models Carry out investigations to evaluate new microarchitectural features and algorithms Correlate models against RTL and post-silicon results Proficient at SW programming with good understanding of C++, C, and Python Qualifications: Bachelor/Masters/Ph.D. degree in Electronics/Computer Engineering or Computer Science with emphasis on computer architecture Additional Information: All your information will be kept confidential according to EEO guidelines.

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