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Software Development Engineer, Elastic Block Storage, Server Durability Engine
Amazon - Tel Aviv-Yafo, Tel Aviv, ISRIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 72 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSoftware Development Engineer, Elastic Block Storage, Server Durability Engine Tel Aviv-Yafo, Tel Aviv, ISR Software Development Engineer - AWS EBS Data Plane - Durability Engine Amazon Web Services is looking for engineers to help us define and build the future of computing. The AWS Elastic Block Store (EBS) service delivers high performance virtualized storage "in the cloud" for EC2. Durable and performant storage is a key building block for any application and as a member of the EBS team you'll work alongside exceptional engineers and leaders to develop and operate one of the largest distributed storage systems in the world. We are looking for a software development engineer for the storage- and durability-focused data plane group that owns core EBS logic and contributes to a broad and strategic set of projects. You will be part of a team of engineers that develop and maintain the components enabling EBS storage, high durability and performance. Key job responsibilities You will collaborate with and learn from the industry's best minds to solve interesting and challenging problems at an enormous scale on a daily basis. This collaboration extends beyond just the team in EBS. You will have the opportunity to work with many other teams in AWS to build a secure, performant, and reliable system. A day in the life The AWS Elastic Block Store (EBS) organization delivers high-performing virtualized storage “in the cloud” for Amazon Web Services. This is a foundational AWS service on which most other AWS services depend. Our team's software
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Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging
Amazon - Austin, Texas, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 140 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $136K-$184K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSignal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging Austin, Texas, USA Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a Signal or Power Integrity Engineer to join our hardware team and contribute to SI/PI analysis and optimization of advanced packaging solutions for next-generation machine learning and data center ASICs. In this role, you will support the package-level signal or power integrity effort - performing detailed simulations, building models, and contributing to design decisions across IC, package, and board boundaries. You'll work closely with senior engineers to help ensure our advanced packaging technologies meet performance, power delivery, and manufacturing targets. Key job responsibilities - Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures under guidance from senior engineers. - Support package stack-up design: assist with dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies. - Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces, or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance). - Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths. - Build
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Sr. Signal Integrity / Power Integrity Engineer, Annapurna Labs, Machine Learning Hardware
Amazon - Austin, Texas, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 167 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $159K-$215K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSr. Signal Integrity / Power Integrity Engineer, Annapurna Labs, Machine Learning Hardware Austin, Texas, USA Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a Senior SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a senior member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Candidates will be successful in this role with these skills: - Strong communication and teamwork skills, with the ability to interact effectively with cross-functional teams. - Decisive, yet collaborative, approach, balancing technical constraints with business and manufacturing considerations. - Problem-solving mindset, able to troubleshoot and resolve SI/PI-related challenges efficiently. Key job responsibilities - Perform end-to-end high-speed channel simulations to ensure signal integrity across complex designs. - Conduct SI/PI analysis to optimize PCB layouts, minimizing losses and signal degradation. - Utilize simulation tools such as ADS, MATLAB, Cadence, HFSS, and others to evaluate performance and troubleshoot issues. - Work with PCIe protocols
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Physical Security Engineer (Design) , Data Center Engineering
Amazon - Dublin, IRLIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 136 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Security From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Surrogacy assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedPhysical Security Engineer (Design) , Data Center Engineering Dublin, IRL AWS Infrastructure Services owns the design, planning, delivery, and operation of all AWS global infrastructure. In other words, we're the people who keep the cloud running. We support all AWS data centers and all of the servers, storage, networking, power, and cooling equipment that ensure our customers have continual access to the innovation they rely on. We work on the most challenging problems, with thousands of variables impacting the supply chain - and we're looking for talented people who want to help. You'll join a diverse team of software, hardware, and network engineers, supply chain specialists, security experts, operations managers, and other vital roles. You'll collaborate with people across AWS to help us deliver the highest standards for safety and security while providing seemingly infinite capacity at the lowest possible cost for our customers. And you'll experience an inclusive culture that welcomes bold ideas and empowers you to own them to completion. Key job responsibilities • Lead designs (construction drawings and specifications) for physical security elements (cameras, access control, intrusion detection, fences, gates, etc.) for DC projects • Using Blue Beam and other drafting technologies to work in collaboration with the design teams to produce designs in Revit (ACC)/CAD. • Coordinating security requirements with all the other disciplines during the design process of a new building / campus (architectural, mechanical, electrical, civil, IT) • Review and direct the work of physical security engineering design consultants • Be the Subject Matter
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Sr. Hardware Development Eng, AWS PCIe & Signal Integrity Team
Amazon - Seattle, Washington, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 98 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $159K-$215K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSr. Hardware Development Eng, AWS PCIe & Signal Integrity Team Seattle, Washington, USA AWS EC2 owns the design, planning, delivery, and operation of all AWS server instances. In other words, we're the people who keep the cloud running. We support all AWS compute, storage, accelerator servers and ensure our customers have continual access to the innovation they rely on. We work on the most challenging problems, with thousands of variables impacting the supply chain - and we're looking for talented people who want to help. You'll join a diverse team of hardware engineers, software engineers, system engineers, technical program managers, and other vital roles. You'll collaborate with people across AWS to help us deliver the highest standards for safety and security while providing seemingly infinite capacity at the lowest possible cost for our customers. And you'll experience an inclusive culture that welcomes bold ideas and empowers you to own them to completion. Key job responsibilities AWS Hardware Engineering is looking for a customer-obsessed, team-driven technology leader to take our engineering of server hardware and software to the next level. As a Hardware Development Engineer on the PCIe and Signal Integrity team within the Core Components Organization, you will work on next-generation high-speed designs for server components and systems. You will be responsible for the success of high-speed, complex PCB designs, particularly PCIe hardware for EC2 servers. Your expertise in high speed PCB design will be crucial as you work with an interdisciplinary team of engineers to develop, validate, launch, monitor
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Silicon Product and Test Engineer
Block, Inc. - Toronto, Ontario, CanadaIndexed from Greenhouse Benefit evidence checked Jun 7, 2026posted 69 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 16 wksource Resolvable source Verified non-birth-parent leave: 16 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSilicon Product and Test Engineer Toronto, Ontario, Canada Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build . Within Proto, our Bitcoin Products team delivers the product and go-to-market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us! The Role We are looking for a Product & Test Engineer to drive post-silicon productization of our bitcoin mining ASICs from silicon bring-up through high-volume manufacturing. This role spans silicon characterization, yield optimization, test strategy development, correlation across multiple platforms, and system-level performance optimization. This is a highly cross-functional role working across ASIC Design, ATE, Bench, Systems, Reliability, Foundry, and OSAT partners. The ideal candidate is hands-on, data-driven, comfortable operating in ambiguity, and excited about building and scaling complex hardware products in a fast-moving environment. You Will - Drive post-silicon bring-up, characterization, qualification, and productization activities from first silicon through mass production. - Develop and optimize wafer sort (CP) and final test (FT) screening strategies to improve power, performance, yield, quality, and DPPM. - Develop, debug, and maintain ATE test
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Hardware Validation Engineer, Networking and Signal Integrity, Platforms
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 65 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $132K-$190K From the posting source Equity Inferred from posting 401(k) reportedHardware Validation Engineer, Networking and Signal Integrity, Platforms Sunnyvale, CA, USA As a hardware validation engineer, you will qualify networking hardware like switches, smart-network interface cards, custom cables, and other specialized hardware for Google's data centers. Google's custom-designed machines make up computing infrastructures in the world. The hardware validation team ensures that this equipment operates properly electrically, functions as intended, meets quality requirements, and exhibits the level of reliability expected by customers. You will work within our lab environments, planning for and executing the required testing. Working with design engineers, you will give inputs on designs to improve our hardware until you're sure it meets Google's standards of quality, reliability, and security. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $132000 - $190000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Create test plans and coordinate resources across
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Hardware Validation Engineer, NPD Hardware
Amazon - Cupertino, California, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 64 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $157K-$213K From the posting source Inferred from posting Adoption assistance Inferred from posting Surrogacy assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedHardware Validation Engineer, NPD Hardware Cupertino, California, USA AWS Infrastructure Services owns the design, planning, delivery, and operation of all AWS global infrastructure. In other words, we're the people who keep the cloud running. We support all AWS data centers and all of the servers, storage, networking, power, and cooling equipment that ensure our customers have continual access to the innovation they rely on. We work on the most challenging problems, with thousands of variables impacting the supply chain - and we're looking for talented people who want to help. You'll join a diverse team of software, hardware, and network engineers, supply chain specialists, security experts, operations managers, and other vital roles. You'll collaborate with people across AWS to help us deliver the highest standards for safety and security while providing seemingly infinite capacity at the lowest possible cost for our customers. And you'll experience an inclusive culture that welcomes bold ideas and empowers you to own them to completion. Amazon Web Services' Network Products Development team is looking for experienced test professionals to help build our next generation networking platforms. The right candidate will play a key role in the design and development of our next generation Ethernet switching platforms for our world class data centers. You will have previous experience testing network products. This includes reviewing designs for testability, developing manufacturing test plans, executing them, troubleshooting issues found during early prototype stages and transition to manufacturing. Compile and analyze production test data using automated data analysis techniques. You
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Software Privacy Engineer, Devices & Services Trust, Privacy, and Accessibility (TPA)
Amazon - Bellevue, Washington, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 108 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $159K-$202K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSoftware Privacy Engineer, Devices & Services Trust, Privacy, and Accessibility (TPA) Bellevue, Washington, USA Devices and Services Trust and Privacy (DSTP) is responsible for maintaining and raising the trust bar for Amazon customers across a diverse set of 30+ Devices and Services (D&S). DSTP offers horizontal services for builders to ensure trust, privacy, and accessibility is built into our products and services. We also build customer-facing capabilities that provides customers with control and transparency and reducing privacy risk, while enabling partner teams to innovate with appropriate guardrails for content moderation, privacy, accessibility, and trust. The DSTP team is looking for a passionate Security and Privacy Incident Response Engineer who can lead the response to privacy and data protection issues across Devices & Services. You must thrive in dynamic/ambiguous situations, and think like both an attacker and defender, while working through the entire incident response lifecycle. You'll be working in a global team environment where clear and accurate communication and collaboration on privacy and data protection issues is critical. In this role, you will apply your creative and critical problem solving skills to quickly contain incidents and then work with cross-functional teams to remediate the root cause. You must have a passion for engineering solutions to complex privacy and data governance challenges, and recognize and fill gaps in capabilities. Above all, you should be passionate about privacy, information security, the ever-changing threat landscape and privacy/security automation and tooling. Key job responsibilities - Manage escalated privacy and trust risk events/cases from start
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Hardware Safety & Compliance Engineer, Hardware Safety & Compliance
Amazon - Sunnyvale, California, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 126 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $135K-$185K From the posting source Inferred from posting Adoption assistance Inferred from posting Surrogacy assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedHardware Safety & Compliance Engineer, Hardware Safety & Compliance Sunnyvale, California, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced devices like Fire tablets, Fire TV, and Echo. What will you help us create? The Role: Hardware safety compliance engineers are responsible for ensuring the company's products meet all relevant safety standards and regulations. They serve as the primary gatekeeper for product safety, conducting thorough reviews to identify and mitigate potential risks. This role is integrated into the product development lifecycle, with the engineers collaborating cross-functionally and utilizing their expertise in safety standards. They perform risk assessments, establish testing protocols, manage certification processes, and interface with regulatory bodies. Beyond compliance, the engineer proactively shapes the safety landscape, setting new industry standards and fostering a strong culture of safety within the organization. This role is a trusted partner and subject matter expert, playing a pivotal role in enabling the company's innovation while prioritizing the safety of its products. Key job responsibilities - Drive a standardized and harmonized approach to Safety Compliance across Amazon's suite of products - Be a technical leader able to utilize deep knowledge and experience to support junior compliance engineers and design teams on safety compliance issues and failures - Determine the applicable regulations, standards, and safety requirements for new and existing products. - Communicate technical safety
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Sr. Principal Embedded System Security Engineer (Onsite - Marlborough, MA) Secret Clearance Required
Raytheon Technologies - US-MA-MARLBOROUGH-MA2 ~ 1001 Boston Post Rd ~ BLDG 2Indexed from Workday Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported Secret clearanceSr. Principal Embedded System Security Engineer (Onsite - Marlborough, MA) Secret Clearance Required US-MA-MARLBOROUGH-MA2 ~ 1001 Boston Post Rd ~ BLDG 2 posted: Posted Yesterday
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Principal Embedded System Security Engineer (Onsite - Marlborough, MA) Secret Clearance Required
Raytheon Technologies - US-MA-MARLBOROUGH-MA2 ~ 1001 Boston Post Rd ~ BLDG 2Indexed from Workday Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported Secret clearancePrincipal Embedded System Security Engineer (Onsite - Marlborough, MA) Secret Clearance Required US-MA-MARLBOROUGH-MA2 ~ 1001 Boston Post Rd ~ BLDG 2 posted: Posted Yesterday
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Senior Director, Global Data Protection & AI Security
Regeneron Pharmaceuticals - SLEEPY HOLLOWIndexed from Workday Benefit evidence checked May 7, 2026posted 66 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 12 wksource Resolvable source Verified non-birth-parent leave: 12 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Director, Global Data Protection & AI Security SLEEPY HOLLOW posted: Posted 4 Days Ago
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Power and Signal Integrity Engineer, PhD Graduate
Google - Tel Aviv, Israel; +1 moreIndexed from Google Custom Benefit evidence checked May 7, 2026posted 176 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPower and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical
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Security Engineer SoC, Devices and Services Security
Amazon - Seattle, Washington, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 128 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $159K-$202K From the posting source Inferred from posting Adoption assistance Inferred from posting Surrogacy assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSecurity Engineer SoC, Devices and Services Security Seattle, Washington, USA The Role Have you wanted an opportunity to find security issues in the chips and low level software that enables various Amazon digital products? Are you able to find bugs in chips by reviewing design and code and by performing tests? This position will provide you with a unique opportunity to do both The Security team is responsible for identifying security flaws and guiding device business to achieve secure hardware architecture for chips used in Amazon devices like Fire TV, Eero, Alexa to name a few. This team partners with business team and performs chip level security testing, secure chip architecture design and advisory, system review, security review for Secure boot code, bootloader code and firmware. In this role, you will: *Help guide the secure development of devices at Amazon, from security design, threat modeling to code reviews, security testing and fuzzing *Propose, research and develop tools and techniques to improve the security posture of devices at scale *Provide technical security expertise and consultation to device product teams *Identify security risks and work with product engineers to create mitigations *Develop new security policies and procedures *Empower others to improve their security acumen by promoting awareness and developing training materials *Participate in projects that develop new intellectual property About the team About AmSec: Diverse Experiences Amazon Security values diverse experiences. Even if you do not meet all of the qualifications and skills listed in the job description, we encourage candidates to
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High-Speed Interface Validation Engineer, Post Silicon Validation
Amazon - Austin, Texas, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 76 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $144K-$194K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedHigh-Speed Interface Validation Engineer, Post Silicon Validation Austin, Texas, USA Annapurna Labs, an AWS organization with development centers in the U.S. and Israel, builds custom silicon and software for AWS customers. Our team combines cloud-scale innovation with world-class expertise across silicon engineering, hardware design, verification, software, and operations to tackle technical challenges that have never been seen before. Join our Post-Silicon Validation team to validate the critical high-speed interconnects - HBM, PCIe, UCIe, and chip-to-chip links - that enable massive bandwidth and scaling in AWS's next-generation ML accelerators. You'll ensure link integrity, performance, and reliability at the electrical and protocol layers across the full product lifecycle, from first silicon through production deployment in AWS data centers. You'll work in a fast-paced, startup-like environment alongside some of the brightest minds in the industry on next generation, internet-scale technology that directly impacts how customers use Machine Learning acceleration. Your expertise will be instrumental in validating the I/O technologies that enable our custom silicon to scale beyond what was previously possible. Key job responsibilities Validate high-speed interfaces (HBM, PCIe, UCIe, custom SerDes) end-to-end from PHY training through sustained traffic Perform electrical characterization: eye diagrams, jitter analysis, voltage margin, and equalization tuning Execute protocol-level compliance testing and interoperability validation against industry specifications Stress-test links across PVT (Process, Voltage, Temperature) corners and aging conditions Debug link training failures, bit errors, and performance degradation using lab instrumentation and silicon debug features Collaborate with PHY design teams on equalization optimization, margin improvement, and silicon feedback A day
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Signal and Power Integrity Engineer
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 69 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $163K-$237K From the posting source Equity Inferred from posting 401(k) reportedSignal and Power Integrity Engineer Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Signal Integrity/Power Integrity (SI/PI) Engineer, you will be responsible for the chip package design with signal/power integrity simulation and characterization in the chip, package and system level. Within a concurrent engineering environment, you will be the main part of a larger team with system architects, ASIC engineers, and other SI/PI engineers. You will work with multi cross-functional teams including chip design team, board design team, system design team as well as vendors. You will drive chip packaging signal and power implementations to meet chip, package and system electrical requirements. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to
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Senior Product Security Engineer
Affirm - Remote CanadaIndexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 62 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Remote From the posting source Security From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $153K-$213K From the posting source Equity Inferred from posting 401(k) reportedSenior Product Security Engineer Remote Canada
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Crypto Systems Engineer
Leidos - Linthicum Heights, MDIndexed from Workday Benefit evidence checked May 7, 2026posted 93 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedCrypto Systems Engineer Linthicum Heights, MD posted: Posted 30+ Days Ago
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Third Party Product Security Engineer
Rockwell Automation - Chennai, IndiaIndexed from Workday Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedThird Party Product Security Engineer Chennai, India posted: Posted Yesterday
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Principal Engineer - IP Verification
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 62 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Engineer - IP Verification Noida posted: Posted Today
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Functional Safety Architect
NXP Semiconductors - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedFunctional Safety Architect 2 Locations posted: Posted Yesterday
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Principal Engineer - IP Verification
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 93 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Engineer - IP Verification Noida posted: Posted 30+ Days Ago
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Principal Engineer - IP Verification
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 91 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Engineer - IP Verification Noida posted: Posted 29 Days Ago
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