Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Benefits

Parental leave

Not verified not verified - source not recorded

Non-birth-parent leave

6 weeks Verified - from the job posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Offered Verified - from the job posting source checked Jun 20, 2026
• Adoption assistance: Offered Verified - from the job posting source checked Jun 20, 2026
• Surrogacy assistance: Not verified

Mental health support

Offered Verified - from the job posting source checked Jun 20, 2026

Relocation assistance

Not verified

Childcare support

Offered Verified - from the job posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$159K-$215K Verified - from the job posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

61% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company Verified - from the job posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging Austin, Texas, USA Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a Sr. Signal & Power Integrity Engineer to join our hardware team and drive the SI/PI analysis and optimization of advanced packaging solutions for next-generation machine learning and data center ASICs. In this role, you will own the package-level signal and power integrity strategy - from early architecture trade-offs through design closure, measurement and validation. You'll work at the intersection of IC, package, and board, ensuring our advanced packaging technologies meet dynamic performance, power delivery, and manufacturing targets. Key job responsibilities - Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures. - Design and optimize package stack-ups: dielectric material selection, impedance control, layer assignment, and RDL routing for high-speed and power delivery performance. - Perform high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces through the package. - Analyze and optimize the package PDN end-to-end: decoupling strategy, plane resonance, IR drop, and AC impedance from die bumps through substrate to board. - Characterize and model on-die capacitance, deep trench capacitors (DTCs), and integrated

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