Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Benefits

Parental leave

6 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

6 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Offered From the posting source checked Jun 20, 2026
• Adoption assistance: Offered From the posting source checked Jun 20, 2026
• Surrogacy assistance: Not verified

Mental health support

Offered From the posting source checked Jun 20, 2026

Relocation assistance

Not verified

Childcare support

Offered From the posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$136K-$184K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

37% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging Austin, Texas, USA Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a Signal or Power Integrity Engineer to join our hardware team and contribute to SI/PI analysis and optimization of advanced packaging solutions for next-generation machine learning and data center ASICs. In this role, you will support the package-level signal or power integrity effort - performing detailed simulations, building models, and contributing to design decisions across IC, package, and board boundaries. You'll work closely with senior engineers to help ensure our advanced packaging technologies meet performance, power delivery, and manufacturing targets. Key job responsibilities - Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures under guidance from senior engineers. - Support package stack-up design: assist with dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies. - Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces, or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance). - Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths. - Build

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