Technical Lead, Digital Design Subsystems

Benefits

Parental leave

18 weeks Source: https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/. source Last checked May 7, 2026.

Non-birth-parent leave

18 weeks Source: https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/. source Last checked May 7, 2026.

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked May 7, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Technical Lead, Digital Design Subsystems Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Lead a team of ASIC RTL engineers on sub-system and activities including: plan tasks, hold code and design reviews, code development of complex features. Interact closely with the Architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and Power, Performance, and Area (PPA) for sub-system integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 10 years of experience working on multiple SoCs with silicon success. 3 years of experience in RTL coding using Verilog or Systemverilog language. Experience in design and multi power domains with clocking. Preferred qualifications: Experience in high performance design, multi power domains with complex clocking. Proficient

Read the full description at www.google.com. FewerJobs shows a preview and links to the original posting.