Senior SI/PI Hardware Engineer, Technical Lead (DDR, PCIe) (Onsite)
Cisco - San Jose, California, US
Posted Jun 6, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
-
- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified checked Jun 13, 2026
- Salary
- $191K-$281K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
Was this benefit information wrong? Tell us.
Market context
- U.S. role benchmark (BLS OEWS)
- $116,543 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
103% above the BLS role benchmark for software engineering aggregate.
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Jun 26, 2026 From the posting source checked Jun 20, 2026
Where they hire
State eligibility is not yet verified.
About this role
Senior SI/PI Hardware Engineer, Technical Lead (DDR, PCIe) (Onsite) San Jose, California, US The application window is expected to close on: 06/26/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you commute to our San Jose, CA office 5 days per week. Meet the Team The Cisco UCS SI team is seeking a Senior Technical Lead, Signal/Power Integrity Engineer for the design and analysis of high-speed interconnects and power distribution networks. As a member of the UCS SI team, you will help develop the next generations of Intel, AMD based Compute Servers for Cisco Blade products, participating in the definition and design of current and next-generation CPUs, ASICs, packages, printed circuit boards (PCBs), and system interconnects. You will be working in a larger team, collaborating closely with Design Hardware Engineers, ECAD, Mechanical, Thermal, Manufacturing, and versatile and knowledgeable SI/PI engineers in the creation of next-generation Compute Server and AI Server products. Your Impact High-speed link modeling and simulation, including high-speed I/O (DDR, PCIe, CXL, UPI, Ethernet etc.), IC package, and system interconnections. Modeling and analyzing power delivery networks. Electromagnetic modeling of complex 3-dimensional structures. Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs using simulations, system level validations, and statistical analysis. Write signal integrity design guidelines, test plans, and test reports. Decide appropriate PCB material, stack-up, and work with vendors to address any DFM (Design for Manufacturability) issues.
Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.
Apply link verified; last checked Aug 3, 2026.
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