ASIC Package Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Package Engineer Taipei, Taiwan Meet the Team We are seeking a skilled and driven ASIC Mechanical Engineer to join Cisco ASIC Group. In this role, you will focus on mechanical and thermomechanical simulations of ASICs and complex silicon packages. Your simulations will directly facilitate product design, ensure mechanical reliability, and accelerate time to market for high-performance Cisco systems. You will collaborate with a globally distributed team across multiple time zones, contributing to innovative, simulation-driven design across packaging, reliability, thermal, and hardware engineering groups. Your Impact · Perform finite element analysis to evaluate thermal mechanical stress, warpage, solder joint reliability of ASIC package, substrates, and advanced packaging assemblies. · Simulate and analyze linear/nonlinear material behaviors, such as plasticity, creep, and viscoelasticity, relevant to solder joints, Copper, stiffener, and underfills. · Develop and automate simulation workflows using Python, Fortran or similar scripting tools to streamline analysis and reporting. · Provide clear simulation results to support mechanical design, root cause analysis, and risk mitigation. · Support design optimization at early phase of product development and failure investigations by correlating FEA predictions with test data and field returns. · Document and present analysis results, assumptions, and design recommendations in a clear, structured format. Minimum Qualifications Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 years of related experience. At least 3 years of experience in mechanical design and thermomechanical simulation of semiconductor packages. Hands-on experience with 3D modeling, finite element analysis using ABAQUS

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.