Senior Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Design Engineer Taiwan Senior SoC FPGA Digital Design and Verification Engineer About Cohu Cohu is a global technology and market leader in semiconductor test and inspection metrology markets. Our advanced systems are critical to ensuring the quality and reliability of the next generation of electronics. This role is a key part of the team developing our state-of-the-art 26 GHz RF semiconductor tester platform , built around the cutting-edge Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) . We need an expert to design and verify the high-performance digital logic that powers this platform. Learn more at cohu.com . The Role: High-Speed RTL and SoC Integration You will be responsible for RTL design , SoC integration , and high-speed timing closure of key digital blocks within the Xilinx Versal ACAP. This role sits at the intersection of hardware and software, requiring deep expertise in digital design best practices, advanced verification methodologies, and a functional understanding of Model-Based Design for DSP implementation. Key Responsibilities RTL Design and Implementation Develop and implement robust, high-performance RTL (Register Transfer Level) using Verilog or SystemVerilog for key functional blocks within the Versal ACAP. Focus on blocks related to high-speed data path, clocking, control, and interaction with the RF front-end. SoC Integration and Bus Interfacing Integrate complex IP blocks and custom logic within the SoC structure, managing data flow across the Versal's Application Processor Fabric and Programmable Logic. Implement and configure AMBA AXI protocols (AXI4-Lite, AXI4-Stream, and AXI4-Full) for efficient system-level communication and data transfer. Verification and

Read the full description at hcbo.fa.us2.oraclecloud.com. FewerJobs shows a preview and links to the original posting.