Senior Design Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Design Engineer Taiwan Senior Digital Verification Engineer About Cohu Cohu is a global technology and market leader in semiconductor test and inspection metrology markets. Our advanced systems are critical to ensuring the quality and reliability of the next generation of electronics. This role is a key part of the team developing our state-of-the-art 26 GHz RF semiconductor tester platform , leveraging cutting-edge Xilinx Versal ACAP technology to achieve unparalleled performance. Learn more at cohu.com . Job Summary Cohu is seeking a Senior Digital Verification Engineer to join our expanding digital team. This critical role focuses on verifying complex digital designs for our power IC, RF, digital, and mixed-signal test solutions within the Versal ACAP. The successful candidate will utilize advanced tools and methodologies-including SystemVerilog (UVM) and Cadence vManager -to develop and execute comprehensive verification plans that ensure first-pass silicon success for our high-performance hardware. Key Responsibilities Verification Strategy and Planning Develop and implement detailed, reusable test plans and verification strategies based on design requirements, architecture specifications, and product functional objectives. Environment Development Create and maintain robust, scalable verification environments using SystemVerilog and the Universal Verification Methodology (UVM) . Test Development and Execution Write, execute, and manage targeted and constrained-random tests to verify functionality at various abstraction levels (unit, block, and full system). Verification IP and Modeling Develop reusable Verification IP (vIP) and Bus Functional Models (BFMs) to accurately simulate and verify interfaces (e.g., AMBA/AXI , I²C , SPI ). Model-Based Verification Implement verification testbenches and comparison points derived from

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