ASIC Verification Engineer - CAG - Taiwan, Taipei

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

ASIC Verification Engineer - CAG - Taiwan, Taipei Taipei, Taiwan Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Meet the Team Are you a recent graduate or early career professional, passionate about cutting-edge technology and eager to gain hands-on experience in the development of high-speed networking chips? Join the Cisco Common ASIC Group as an ASIC Verification Engineer. This role offers a unique opportunity to contribute to crafting the ASICs that power the world's data flow every time someone connects online. Your Impact Develop and maintain advanced test benches and verification environments using System Verilog and UVM. Execute the end-to-end verification process of complex ASIC design blocks. Develop comprehensive test plans and coverage points to ensure robust verification. Implement the upgrade and refinement of test benches to integrate new features seamlessly. Collaborate with cross-functional teams for thorough cross-block verification and top-level integration. Minimum Qualifications: Bachelor's or Master's degree in Electrical & Electronics Engineering (EE) or Computer Engineering (CE). 0-3 years of experience in ASIC verification (including relevant internships or academic projects). Strong knowledge in Digital Design and ASIC flow. Proficiency in System Verilog-based verification. Preferred Qualifications: Familiarity with UVM. Eagerness to learn and a proactive approach to problem-solving. Excellent team working skills, with the ability to collaborate effectively with colleagues across different functions. Self-driven mindset with a commitment

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