ASIC Design Engineer, STA

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$152K-$219K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

59% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Apr 30, 2026 From the posting source checked Jun 20, 2026

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Engineer, STA San Jose, California, US The application window is expected to close on: 04/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Within this role, you'll work on closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while handling ECO tasks. Your Impact As an ASIC Design Engineer on the STA team, you will play a pivotal role in extraction and static timing analysis (STA) flow development, convergence strategies, and correlation between PNR, Spice, and STA, while working alongside the Physical Design team. Develop methodologies, guidelines, and checklists to streamline STA work. Resolve design and flow issues Drive execution to ensure progress and accuracy. Minimum Qualifications Bachelor's degree in Electrical or Computer engineering and 5+ years of ASIC Design experience, or Master's degree in Electrical or Computer Engineering and 3+ years of experience, or PhD + 0 years of experience. Experience with Verilog/SystemVerilog programming. Preferred Qualifications Prior STA experience

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