CPU Processor Performance Verification Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work

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Application

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Deadline

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About this role

CPU Processor Performance Verification Engineer Santa Clara, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this highly visible role, you will be at the center of a chip design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly. You will be responsible for silicon performance verification, correlation, characterization and tuning for CPUs. The role involves pre-silicon performance verification as well as developing tests to characterize CPU performance, analyzing and profiling software/applications, correlating and comparing performance across silicon/system software version, and working with OS and compiler teams on performance debug and tuning. As a CPU Processor Performance Verification Engineer owning the verification of a certain area of performance features in a chip design, you will have responsibilities as follows: • Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon)

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