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  • Principal Project Engineer, Avionics FPGA/ASIC (Onsite)

    Raytheon Technologies - US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 92 days ago

    Why we showed this

    Employer: semantic matchEmployer: "technologies"
    +2
    Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Principal Project Engineer, Avionics FPGA/ASIC (Onsite) US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121 posted: Posted 30+ Days Ago

  • Associate Director – AI Software, Applied Research & Technology – Defense Technologies (Onsite)

    Raytheon Technologies - US-IA-CEDAR RAPIDS-108 ~ 400 Collins Rd NE ~ BLDG 108
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 92 days ago

    Why we showed this

    Description: "technologies"Employer: "technologies"
    +3
    Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Associate Director – AI Software, Applied Research & Technology – Defense Technologies (Onsite) US-IA-CEDAR RAPIDS-108 ~ 400 Collins Rd NE ~ BLDG 108 posted: Posted 30+ Days Ago

  • Sr Electrical Engineer - ASIC/FPGA (Onsite)

    Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 75 days ago

    Why we showed this

    Employer: semantic matchEmployer: "technologies"
    +2
    Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Sr Electrical Engineer - ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago

  • Welder II (Onsite)

    Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 77 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Onsite - 5d office From the posting source Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Welder II (Onsite) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 16 Days Ago

  • Mechanical Assembler II (Onsite)

    Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 77 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Onsite - 5d office From the posting source Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Mechanical Assembler II (Onsite) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 16 Days Ago

  • Assembler II (2nd Shift)

    Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 75 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Unspecified Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Assembler II (2nd Shift) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 14 Days Ago

  • Assembler II (1st Shift)

    Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 75 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Unspecified Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Assembler II (1st Shift) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 14 Days Ago

  • Senior Systems Engineer - Onsite Cambridge MA

    Raytheon Technologies - US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site)
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 65 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Onsite - 5d office From the posting source Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Systems Engineer - Onsite Cambridge MA US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site) posted: Posted 4 Days Ago

  • Assembler II (3rd Shift)

    Raytheon Technologies - US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 75 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Unspecified Trades From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Assembler II (3rd Shift) US-TX-SAN MARCOS-2005 ~ 2005 Technology Wy ~ TECHNOLOGY posted: Posted 14 Days Ago

  • Technology Director - Integrated Manufacturing Technologies - Aerospace Research

    GE Aerospace - Niskayuna
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 92 days ago

    Why we showed this

    Description: "technologies"Title: "technologies"
    +2
    Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Technology Director - Integrated Manufacturing Technologies - Aerospace Research Niskayuna posted: Posted 30+ Days Ago

  • Principal Systems Engineer Onsite - Cambridge MA

    Raytheon Technologies - US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site)
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 62 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Onsite - 5d office From the posting source Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Principal Systems Engineer Onsite - Cambridge MA US-MA-CAMBRIDGE-555-CUST ~ 555 Technology Sq ~ TECHNOLOGY (External Site) posted: Posted Yesterday

  • Leader qualité et des technologies de données | Quality Operation Lead and Data Technologies

    Raytheon Technologies - CA-QC-LONGUEUIL-J01 ~ 1000 Blvd Marie-Victorin ~ J01 BLDG
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 61 days ago

    Why we showed this

    Description: "technologies"Employer: "technologies"
    +3
    Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Leader qualité et des technologies de données | Quality Operation Lead and Data Technologies CA-QC-LONGUEUIL-J01 ~ 1000 Blvd Marie-Victorin ~ J01 BLDG posted: Posted Today

  • Technology & Digital

    Kroger - Location not specified
    Indexed from Oraclecloud Benefit evidence checked May 7, 2026
    posted 68 days ago

    Why we showed this

    Title: semantic matchSource-backed benefits
    +1
    Unspecified Marketing From the posting source - Mid From the posting source Resolvable source Verified parental leave: 2 wksource Resolvable source Verified non-birth-parent leave: 2 wksource Salary not disclosed Equity

    Technology & Digital Technology & Digital

  • Digital Technology Manager

    Raytheon Technologies - 2 Locations
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 92 days ago

    Why we showed this

    Employer: "technologies"Employer: semantic match
    +1
    Unspecified Marketing From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Digital Technology Manager 2 Locations posted: Posted 30+ Days Ago

  • Sr. Acoustic Software QA Engineer, Asia Tech Center

    Amazon - Shenzhen, CHN
    Indexed from Amazon Custom Benefit evidence checked Jun 7, 2026
    posted 65 days ago

    Why we showed this

    Title: semantic matchRole: semantic match
    +1
    Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reported

    Sr. Acoustic Software QA Engineer, Asia Tech Center Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Acoustic Software QA Engineer, you will work with consumer application testing expertise. You will join the team of hands-on, pro-active, self-motivated and seasoned SQA professionals. In this role, you will: - Create test plans and test cases - Efficiently execute test cases across all functional areas of our products especially have expertise in Audio. - Review product user interface for conformity to design guidelines - Find, isolate, document, regress, and track bugs through resolution - Interpret and report testing results, and be a vocal proponent for quality in every phase of the development process - Work with Software Development Engineers to understand the overall technical architecture and how each feature is implemented - Collaborate with US teams and domestic partners in acoustic lab setting up and management Basic Qualifications: - 4+ years of quality assurance engineering experience - Experience scripting or coding - Knowledge of QA methodology, industry-standard tools and bug tracking tools - Familiarity with acoustic performance measurement and equipment - Familiarity with acoustic lab environment setup Preferred Qualifications: - Experience in testing and QA environments - Familiarity with ACQUA

  • Sr. Manager, Finance Technology & Transformation

    Salesforce - Ireland - Dublin
    Indexed from Phenom Umbraco Benefit evidence checked May 7, 2026
    posted 237 days ago

    Why we showed this

    Description: "technologies"Description: semantic match
    +1
    Unspecified Finance From the posting source - Senior From the posting source Resolvable source Verified parental leave: 26 wksource Inferred from posting Verified non-birth-parent leave: 12 wk Salary not disclosed Equity Inferred from posting 401(k) reported

    Sr. Manager, Finance Technology & Transformation Ireland - Dublin The Controlership team is seeking an experienced finance technology leader to drive digital transformation initiatives and deliver innovative solutions that enhance operational efficiency, compliance, and strategic decision-making across our organization. Position Summary We are looking for an accomplished Senior Manager to join our Finance Technology and Innovation function, reporting directly to the Senior Director of Finance Technology and Innovation. This role requires a strategic thinker with deep expertise in finance operations, technology solutioning, and project delivery. The ideal candidate will have a proven track record of leveraging emerging technologies, including AI/ML, to streamline processes, reduce costs, and deliver measurable business value while collaborating closely with leadership to execute the team's vision. Strategic Leadership & Transformation Support enterprise-wide finance technology transformation initiatives that align with organizational strategic goals Collaborate with executive leadership and the Controllership Operations team to identify opportunities for technology-enabled process improvements Contribute to change management efforts to ensure smooth adoption of new technologies and processes Help execute the technology roadmap for the Controllership and broader Finance organization Technology Innovation & Implementation Evaluate, recommend, and implement cutting-edge technologies including Agents, AI/ML, automation tools, and advanced analytics platforms Manage and deliver technology projects that improve efficiency, compliance, accuracy, and operational insights Contribute to innovation programs that encourage experimentation and adoption of emerging technologies Provide insights and recommendations to senior finance leadership on technology strategy and process enhancement opportunities Team Leadership & Development Manage and mentor team members and project workstreams Foster

  • Business Technology Partner Manager Process Transformation Procurement

    Bunge - Sant Just Desvern
    Indexed from Successfactors Benefit evidence checked May 7, 2026
    posted 60 days ago

    Why we showed this

    Title: semantic matchSource-backed benefits

    Business Technology Partner Manager Process Transformation Procurement Sant Just Desvern Requisition Number: 44361 We are seeking a highly business‑centric Business Technology Partner Manager Process Transformation Procurement, with a primary focus on Procurement and Finance. This role serves as the strategic interface between Corporate leadership and Business Technology, ensuring that technology investments, roadmaps, and delivery outcomes are fully aligned with enterprise financial objectives, governance standards, and global operating models. The BTP is accountable for translating Procurement and Finance strategies into a clear, prioritized Business Technology roadmap; coordinating delivery through global product and technology teams; and ensuring measurable business value through agreed OKRs and performance metrics. This role partners closely with senior leaders across Procurement, Finance, Internal Controls, and Shared Services, as well as Business Technology product, architecture, and delivery teams. Main Accountabilities: Act as the primary Business Technology point of contact for Corporate Procurement and Finance leadership. Develop a deep understanding of Procurement and Finance strategies, operating models, regulatory and control requirements, and transformation priorities. Translate business strategy and functional needs into a clear, value‑driven Business Technology roadmap aligned with enterprise architecture, global standards, and investment governance. Proactively identify, propose, and drive technology‑enabled initiatives to improve Procurement an

  • Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices

    Amazon - Shenzhen, CHN
    Indexed from Amazon Custom Benefit evidence checked Jun 7, 2026
    posted 78 days ago

    Why we showed this

    Description: semantic matchDescription: "technologies"
    +2
    Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reported

    Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies

  • Senior Manager, Finance Technology & Transformation

    Salesforce - Canada - Toronto
    Indexed from Phenom Umbraco Benefit evidence checked May 7, 2026
    posted 137 days ago

    Why we showed this

    Description: "technologies"Description: semantic match
    +1
    Unspecified Finance From the posting source - Senior From the posting source Resolvable source Verified parental leave: 26 wksource Inferred from posting Verified non-birth-parent leave: 12 wk Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Manager, Finance Technology & Transformation Canada - Toronto The Controlership team is seeking an experienced finance technology leader to drive digital transformation initiatives and deliver innovative solutions that enhance operational efficiency, compliance, and strategic decision-making across our organization. Position Summary We are looking for an accomplished Senior Manager to join our Finance Technology and Innovation function, reporting directly to the Senior Director of Finance Technology and Innovation. This role requires a strategic thinker with deep expertise in finance operations, technology solutioning, and project delivery. The ideal candidate will have a proven track record of leveraging emerging technologies, including AI/ML, to streamline processes, reduce costs, and deliver measurable business value while collaborating closely with leadership to execute the team's vision. Strategic Leadership & Transformation Support enterprise-wide finance technology transformation initiatives that align with organizational strategic goals Collaborate with executive leadership and the Controllership Operations team to identify opportunities for technology-enabled process improvements Contribute to change management efforts to ensure smooth adoption of new technologies and processes Help execute the technology roadmap for the Controllership and broader Finance organization Technology Innovation & Implementation Evaluate, recommend, and implement cutting-edge technologies including Agents, AI/ML, automation tools, and advanced analytics platforms Manage and deliver technology projects that improve efficiency, compliance, accuracy, and operational insights Contribute to innovation programs that encourage experimentation and adoption of emerging technologies Provide insights and recommendations to senior finance leadership on technology strategy and process enhancement opportunities Team Leadership & Development Manage and mentor team members and project workstreams Foster

  • Sr. RF Hardware Systems Engineer

    Samsara - San Francisco - SF9
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 62 days ago

    Why we showed this

    Title: semantic matchRole: semantic match
    +1
    Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 16 wksource Inferred from posting Verified non-birth-parent leave: 16 wk $177K-$240K From the posting source Inferred from posting Childcare support Inferred from posting Mental health support Inferred from posting Learning budget Equity Inferred from posting 401(k) reported

    Sr. RF Hardware Systems Engineer San Francisco - SF9 Who we are Samsara (NYSE: IOT) is the pioneer of the Connected Operations™ Cloud, which is a platform that enables organizations that depend on physical operations to harness Internet of Things (IoT) data to develop actionable insights and improve their operations. At Samsara, we are helping improve the safety, efficiency and sustainability of the physical operations that power our global economy. Representing more than 40% of global GDP, these industries are the infrastructure of our planet, including agriculture, construction, field services, transportation, and manufacturing - and we are excited to help digitally transform their operations at scale. Working at Samsara means you'll help define the future of physical operations and be on a team that's shaping an exciting array of product solutions, including Video-Based Safety, Vehicle Telematics, Apps and Driver Workflows, and Equipment Monitoring. As part of a recently public company, you'll have the autonomy and support to make an impact as we build for the long term. About the role We're looking for a Senior Hardware Engineer, RF Systems to own critical RF subsystems and help define platform‑level RF architectures that power Samsara's connected hardware portfolio. You'll combine deep RF expertise with strong product instincts, partnering with cross‑functional teams to ship robust, high‑volume hardware. Our hardware team owns end‑to‑end product development for Samsara's AI & Connected devices, from architecture and component selection through validation and ramp to mass production. Within this team, you will lead RF and wireless architectures and

  • Senior RFIC Design Engineer

    Analog Devices - Turkey, Istanbul, Bilisim Vadisi
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 92 days ago

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    Title: semantic matchRole: semantic match
    +1
    Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior RFIC Design Engineer Turkey, Istanbul, Bilisim Vadisi posted: Posted 30+ Days Ago

  • ASIC Design Engineer, Amazon Camera ASIC Team

    Amazon - Cambridge, England, GBR
    Indexed from Amazon Custom Benefit evidence checked Jun 7, 2026
    posted 125 days ago

    Why we showed this

    Title: semantic matchRole: semantic match
    +1
    Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reported

    ASIC Design Engineer, Amazon Camera ASIC Team Cambridge, England, GBR Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Write micro-architecture specs and solicit feedback/link to KPIs from architecture team - Execute on design specifications to deliver high quality RTL - Evaluate 3rd party IP blocks - Estimate power, performance, and area for significant IPs early in design cycle - Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans Basic Qualifications: - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience with front-end design tools (Lint, CDC, RDC and lint) - Ability to write detailed micro-architectural specs which work through the design problems before coding (System Verilog, Verilog). Preferred Qualifications: - Bachelor's degree in Electrical or Communications Engineering or a related field - Experience with industry standard tools and scripting languages (Python

  • Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

    Amazon - Austin, Texas, USA
    Indexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 138 days ago

    Why we showed this

    Title: semantic matchRole: semantic match
    +1
    Unspecified Design From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $159K-$215K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reported

    Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs Austin, Texas, USA Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a foundational role in the project by automating design flows and building large-scale solutions that accelerate silicon development and we're just getting started here at Amazon! We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality. Key job responsibilities Core Responsibilities: - Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards. - Enhance and build design flows to boost the overall productivity of design teams. - Collaborate with vendors to evaluate and qualify new design tools and updated tool versions. About the team Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks

  • Senior ASIC RTL Engineer, Silicon

    Google - Bengaluru, Karnataka, India
    Indexed from Google Custom Benefit evidence checked May 7, 2026
    posted 83 days ago

    Why we showed this

    Description: semantic matchDescription: "technologies"
    +2
    Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior ASIC RTL Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in

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