ASIC Design Engineer, Amazon Camera ASIC Team

Benefits

Parental leave

6 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

6 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Offered From the posting source checked Jun 20, 2026
• Adoption assistance: Offered From the posting source checked Jun 20, 2026
• Surrogacy assistance: Not verified

Mental health support

Offered From the posting source checked Jun 20, 2026

Relocation assistance

Not verified

Childcare support

Offered From the posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Engineer, Amazon Camera ASIC Team Cambridge, England, GBR Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Write micro-architecture specs and solicit feedback/link to KPIs from architecture team - Execute on design specifications to deliver high quality RTL - Evaluate 3rd party IP blocks - Estimate power, performance, and area for significant IPs early in design cycle - Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon verification teams to assist in defining test-plans/test-benches - Work with post-silicon validation teams to define and execute on test-plans Basic Qualifications: - Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills - Experience with front-end design tools (Lint, CDC, RDC and lint) - Ability to write detailed micro-architectural specs which work through the design problems before coding (System Verilog, Verilog). Preferred Qualifications: - Bachelor's degree in Electrical or Communications Engineering or a related field - Experience with industry standard tools and scripting languages (Python

Read the full description at www.amazon.jobs. FewerJobs shows a preview and links to the original posting.