Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs
Amazon - Austin, Texas, USA
Posted Mar 27, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Mental health support
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- Salary
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- 401(k) match
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Schedule
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Application
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Where they hire
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About this role
Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs Austin, Texas, USA Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer, you'll play a foundational role in the project by automating design flows and building large-scale solutions that accelerate silicon development and we're just getting started here at Amazon! We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality. Key job responsibilities Core Responsibilities: - Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards. - Enhance and build design flows to boost the overall productivity of design teams. - Collaborate with vendors to evaluate and qualify new design tools and updated tool versions. About the team Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks
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