Block, Inc. jobs

Senior Product Manager, Block Storage Bengaluru, Karnataka, India At Google, we put our users first. The world is always changing, so we need Product Managers who are continuously adapting and excited to work on products that affect millions of people every day. In this role, you will work cross-functionally to guide products from conception to launch by connecting the technical and business worlds. You can break down complex problems into steps that drive product development. One of the many reasons Google consistently brings innovative, world-changing products to market is because of the collaborative work we do in Product Management. Our team works closely with creative engineers, designers, marketers, etc. to help design and develop technologies that improve access to the world's information. We're responsible for guiding products throughout the execution cycle, focusing specifically on analyzing, positioning, packaging, promoting, and tailoring our solutions to our users. In this role, you will be responsible for the product definition and success for backup products within the block storage portfolio, ensuring that GCE customers, critical Google Cloud Platform (GCP) services, and GCP partners are positioned for success with data protection and business continuity. As GCE Block Storage continues to grow, there is a consistent need to deliver outstanding next-generation capabilities and efficiency. You will have experience with compute and storage cloud infrastructure, and experience working with enterprise and cloud-native customers to drive success. Additionally you will be creative and have excellent communication skills. Google Cloud accelerates every organization's ability to digitally transform its business

Intern, Textile Engineering Haryana, Gurugram International Techpark, Block I Phase 1 Floors G, 3, 4, 5 posted: Posted 28 Days Ago

Area Sales Manager-Bangalore Haryana, Gurugram International Techpark, Block I Phase 1 Floor 6 posted: Posted 30+ Days Ago

Area sales Manager-Coimbatore Haryana, Gurugram International Techpark, Block I Phase 1 Floor 6 posted: Posted 30+ Days Ago

Medical Writer Haryana, Gurugram International Techpark, Block I Phase 1 Floors G, 3, 4, 5 posted: Posted 9 Days Ago

Customer Account Executive SG-01-SINGAPORE-041 BLOCK A ~ 41 Changi N CRES ~ 41 CHANGI N CRES-041 BLOCK A posted: Posted 30+ Days Ago

Assembly, Repair, Maintenance & Overhaul Electro-mechanical Technician - Wireline AE-ABU DHABI-MUSSAFAH ATLAS MW4C BLOCK 10B posted: Posted 8 Days Ago

Engineer RGA Tech Park, 2nd floor Block-2, Survey # 31/1, Chikkannhelli Village, Varthur Hobli, Bangalore East Taluk, Bangalore - 560035, India posted: Posted Yesterday

Technician II SG-01-SINGAPORE-041 BLOCK A ~ 41 Changi N CRES ~ 41 CHANGI N CRES-041 BLOCK A posted: Posted Today

Delivery Staff - Ho Chi Minh Vietnam > Ho Chi Minh : Lot 6-1A, Block 6, Warehouse 18, M1 Road, Tan Binh Industrial Park posted: Posted 7 Days Ago

Spclst, Prod&Tech Svc-1 RGA Tech Park, 2nd floor Block-2, Survey # 31/1, Chikkannhelli Village, Varthur Hobli, Bangalore East Taluk, Bangalore - 560035, India posted: Posted Yesterday

Senior Engineer RGA Tech Park, 2nd floor Block-2, Survey # 31/1, Chikkannhelli Village, Varthur Hobli, Bangalore East Taluk, Bangalore - 560035, India posted: Posted 17 Days Ago

Mechanic CN-SH-SHANGHAI-008 ~ No 8 Block 1 8228 Beiqing Hwy ~ BEIQING posted: Posted 30+ Days Ago

Operations Specialist Bogotá, Bogota, Colombia Company Description: About AbbVie AbbVie's mission is to discover and deliver innovative medicines and solutions that solve serious health issues today and address the medical challenges of tomorrow. We strive to have a remarkable impact on people's lives across several key therapeutic areas including immunology, oncology and neuroscience - and products and services in our Allergan Aesthetics portfolio. For more information about AbbVie, please visit us at www.abbvie.com . Follow @abbvie on LinkedIn, Facebook , Instagram , X and YouTube. Job Description: The Operations Specialist is responsible for ensuring the efficient execution, control, and continuous improvement of key finance operations processes within the Shared Service Center, including Concur, P2P, fleet management, employee benefits, and related service activities. This role ensures compliance with internal policies, local regulations, global standards, and service level agreements, while driving operational excellence, stakeholder alignment, and process improvement across the function. Qualifications: Define, document, and maintain standard operating procedures for finance operations processes within the service center. Manage end-to-end processes ensuring accuracy, timeliness, compliance, and adherence to approved workflows and SLAs. Oversee Concur processes, ensuring expense reports and credit card transactions are resolved in accordance with global and local compliance standards. Manage P2P processes, including monitoring blocked invoices, open PO aging, and required follow-up actions. Ensure fleet management processes comply with global standards, local regulations, and internal policies. Monitor vehicle inventory, documentation, taxes, maintenance schedules, and logbook records on a monthly basis. Establish and maintain internal controls to ensure governance, compliance, and

Associate Engineer - Fullstack (Hybrid) IN-TS-HYDERABAD-B3F7 ~ DLF Cybercity Gachibowli ~ DLF CYBERCITY GACHIBOWLI-B3F7, 7th Fl in Block 3 posted: Posted Yesterday

Senior ASIC RTL Integration Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering

ASIC RTL Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical

ASIC RTL Design Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/ Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer

Full Chip Front-End DFT Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define and document the Design for Testability (DFT) architecture for multi-core System on Chips (SoCs), including strategies for hierarchical scan compression, MBIST (Memory BIST), Logic BIST and Analog Mixed Signal circuits. Implement DFT logic, boundary scan, MBIST, scan chains, DFT compression, Clock Control block, and other DFT Internet Protocol (IP) blocks. Work with the Register Transfer Level (RTL) and Physical Design (PD) team at SoC level, and with the subsystem DFT teams. Write scripts to automate the DFT flow. Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow. Minimum qualifications: Bachelor's degree in Science or Electrical or Electronics Engineering or a related technical field or equivalent practical experience. 5 years of experience with ATPG, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. 3

Design Verification Engineer, Multimedia, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using System Verilog and UVM. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with verification methodologies and languages such as UVM or SystemVerilog. Experience with object oriented programming. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture,

Silicon Design Verification Engineer Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $116000 - $166000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan the verification of digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios. Develop and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Design and implement comprehensive coverage measures to target functional stimulus and corner-case scenarios. Debug test failures in collaboration with design engineers to ensure functionally correct digital blocks. Analyze coverage data to identify verification gaps and track progress toward tape-out milestones. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience. 1 year of experience verifying

Design Verification Engineer Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices and Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices and Services team is making people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or verify designs with SystemVerilog Assertions (SVA) and formal tools. Debug tests with design engineers to deliver design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Identify and write all types

Design Verification Engineer, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $138000 - $198000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios. Develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Design and implement comprehensive coverage measures to target functional stimulus and corner-case scenarios. Debug test failures in collaboration with design engineers to ensure functionally correct digital blocks. Analyze coverage data to identify verification gaps and track progress toward tape-out milestones. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience verifying

Junior SOC Design Verification Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Junior SoC Design Verification Engineer, you will develop and execute efficient verification strategies ranging from planning and constrained random testing to debugging and closure while collaborating with engineers to validate digital designs across the life-cycle. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios. Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs using SVA and formal tools. Identify and define all relevant coverage measures to address design corner-cases. Debug tests with design engineers to ensure functionally correct design blocks. Close coverage gaps to identify verification holes and demonstrate progress towards tape-out. Minimum qualifications: Bachelor's