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Silicon Design Verification Engineer

Google - Mountain View, CA, USA

Posted Jun 5, 2026

Benefits

Parental leave
18 weeks From the posting source checked Jun 20, 2026
Non-birth-parent leave
18 weeks From the posting source checked Jun 20, 2026
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Source-linked checked May 7, 2026
Salary
$116K-$166K From the posting source checked Jun 20, 2026
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

21% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Silicon Design Verification Engineer Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $116000 - $166000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan the verification of digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios. Develop and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Design and implement comprehensive coverage measures to target functional stimulus and corner-case scenarios. Debug test failures in collaboration with design engineers to ensure functionally correct digital blocks. Analyze coverage data to identify verification gaps and track progress toward tape-out milestones. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience. 1 year of experience verifying

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