Junior SOC Design Verification Engineer, Google Cloud
Google - Tel Aviv, Israel; +1 more
Posted May 15, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Source-linked last checked May 7, 2026
- Salary
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- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked May 7, 2026.
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Schedule
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- Weekend work
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Application
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- Assessment
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- Deadline
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Where they hire
State eligibility is not yet verified.
About this role
Junior SOC Design Verification Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Junior SoC Design Verification Engineer, you will develop and execute efficient verification strategies ranging from planning and constrained random testing to debugging and closure while collaborating with engineers to validate digital designs across the life-cycle. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Plan verification of digital design blocks by understanding specifications and collaborating with design engineers to identify key scenarios. Develop and refine constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs using SVA and formal tools. Identify and define all relevant coverage measures to address design corner-cases. Debug tests with design engineers to ensure functionally correct design blocks. Close coverage gaps to identify verification holes and demonstrate progress towards tape-out. Minimum qualifications: Bachelor's
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