Astera Labs jobs

System Validation Engineer (NCG 2026) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions-built on PCIe®, CXL™, Ethernet, and custom fabrics-enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms. Role Overview As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs . You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams. Key Responsibilities - Execute system validation test plans for Taurus Ethernet Smart Cable Modules. - Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches - Validate high-speed interconnects and

Staff/ Principal Architect Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview We are seeking an experienced Staff/ Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems. This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design . You will play a key role

Hardware Design Engineering, Director - Active Electric Cable / Smart Cable Module Business - China Shanghai Shi, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Director, Hardware Design Engineering - AEC / SCM & China Customer Support Reports to: Senior Director, Hardware Design Engineering Location: Shanghai, China - Astera Labs Shanghai Design Center About Astera Labs Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our AEC and SCM product lines scale rapidly to meet hyperscale AI infrastructure demand - and as China-based OEM customers, hyperscale cloud providers, and system integrators increasingly adopt Astera Labs silicon and connectivity products - we are establishing a Shanghai-based hardware design center to drive product development, manufacturing collaboration, and customer engineering support in close proximity to our manufacturing partners and China-based customers. About the Role We are hiring a Director

DFT Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable.

Senior Strategic Procurement Specialist - Corporate Services & Facilities Operations Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, Astera Labs is seeking a hands-on Senior Strategic Procurement Specialist & Facilities Operations to support regional procurement activities across a growing set of international sites. This role is responsible for executing day-to-day sourcing, vendor management, and procurement operations to support labs, facilities, and office expansion. You will act as the primary procurement point of contact for your region, working closely with engineering, IT, facilities, and operations teams to ensure timely vendor onboarding, material availability, and resolution of purchasing issues. This role is critical to enabling site ramp and ongoing operations as Astera scales globally. Key Responsibilities - Strategic procurement specialist -

Staff DFT Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Staff DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is

Senior/Staff Physical Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person. Basic Qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer is required, and a Master's degree is preferred. - ≥3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in

Physical Design Engineer (Place & Route) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person. Basic Qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred. - 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and

Senior Manager of Corporate Development San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? Astera Labs is seeking a Senior Manager of Corporate Development to lead and support strategic transactions including acquisitions, investments, and strategic partnerships that will shape the future of AI connectivity. In this high-visibility role, you will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be at the forefront of emerging AI infrastructure technologies, developing new business models and driving transactions that accelerate our position as the leader in purpose-built connectivity solutions. This is a unique opportunity to join a hyper-growth company at the intersection of semiconductors and AI infrastructure, where your work will directly influence strategic decisions and contribute

Sr. Director of Product Marketing San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Director of Product Marketing to lead go-to-market strategy for our industry-leading fabric switch and memory controller solutions. This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our connectivity products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate customers' needs into competitive roadmaps and compelling value propositions that resonate with decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape

Lead Firmware Engineer Shanghai Shi, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs' SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs' products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended. Basic qualifications - Strong academic and technical background in Electronics/Electrical/Computer Science engineering. At a minimum, a Bachelor's is required, and a Master's is preferred. - Minimum 5 years' experience supporting or developing complex SoC /silicon products for Server, Storage, and/or Networking applications. - Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC ). - Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs. - Professional attitude with

Physical Design/CAD Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person. Key Responsibilities - As Physical Design CAD Engineer you will support and build flows for world class EDA tools. - Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. - Architect and recommend flow improvements and enhance existing methodology for high performance design. - Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. - Work with cross function teams to define requirements and specifications

Lead Product Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Tech Lead Product Engineer to join our team in San Jose, CA. In this role, you will be at the intersection of silicon development and production excellence, ensuring our industry-leading connectivity solutions meet the highest standards of performance, reliability, and quality as they scale to volume production. As a key technical contributor, you will own the RF and signal integrity aspects of product engineering - from silicon characterization and validation through production test development and customer-facing debug. You'll work across the full product lifecycle, partnering with design, applications, and operations teams to drive our connectivity products from tape-out to high-volume manufacturing. This is a high-impact role at a company experiencing explosive growth, where your work directly enables the AI infrastructure revolution. With Astera Labs' portfolio spanning PCIe retimers, Ethernet solutions, and next-generation switching silicon operating at the bleeding edge of SerDes performance,

Firmware Engineering Director/ Manager San Jose Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview As a Firmware Engineering Director/ Manager , you will lead and scale firmware development efforts for Astera Labs' SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development. Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs. This role supports two leadership levels: - Firmware Engineering Manager - Firmware Engineering Director Key Responsibilities - Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps. - Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers. - Provide technical oversight and architectural guidance without being the

Sr. Principal Product Marketer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal, Product Marketing to serve as the strategic marketing leader for our Leo Smart Memory Extender product line - the industry's most advanced CXL-based solution enabling memory expansion and disaggregation for AI and cloud infrastructure at rack scale. This is a senior individual contributor role with outsized influence, where you'll define how the market understands, evaluates, and adopts CXL memory technology. As AI models scale to hundreds of billions of parameters and memory capacity becomes the defining bottleneck in modern data centers, Leo is uniquely positioned to unlock new levels of performance and efficiency. In this role, you'll operate as the authoritative voice of the Leo product line - shaping narratives that influence hyperscaler architecture decisions, driving industry thought leadership, and partnering with Astera Labs' most senior technical and business leaders to accelerate market creation. This is a

Executive Sales Representative Taipei, Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Regional Sales Executives will work closely with Field Sales Engineers (FAEs) and the sales management team to develop and execute an account strategy to effectively engage with leading cloud service providers on Astera Labs' portfolio of connectivity products. Responsibilities - Develop a customer specific sales plan that identifies revenue generating opportunities and outlines steps to effectively develop relationships within key influencers in R&D, Procurement, Executive level GM/CTO - Drive sales efforts by teaming up with FAEs engaging with customers to provide roadmap updates, technology training, product sampling, technical support and gather customer forecasts - Be a strong voice for your customers to communicate their product roadmap feedback, customer support issues and to drive a timely response from Astera Labs HQ - Establish regular communication with your customer's procurement, ODM ecosystem and other industry partners to be able to accurately forecast your region's quarterly revenue and annual demand forecast Qualifications - Bachelor's

Principal AEC / AOC Program Manager Suzhou Qu, Gansu, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs Principal AEC / AOC Program Manager you will play a crucial role in overseeing the planning, coordination, and execution of manufacturing projects featuring Astera Labs' AEC / AOC portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. You will ensure that production processes run smoothly, meet quality standards, and are completed on time and within budget and responsible for manufacturing from NPI to mass production phases. To accomplish that, you will be working closely with designers, the manufacturing team, suppliers, and contract manufacturers. This role is expected to travel up to 30% of the year and will require business English skills. Job Responsibilities - Project Planning and Execution - Develop Project Plans: Create detailed project plans, including schedules, budgets, resource allocation, and timelines. - Coordinate Production Activities: Oversee all aspects of the manufacturing process,

Director Product Marketing - Signal Connectivity Products San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Director of Product Marketing to lead go-to-market strategy for our industry-leading connectivity solutions . This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our PCIe signal conditioning products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate deep technical capabilities into compelling value propositions that resonate with technical decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the

Benefits Manager San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a strategic and knowledgeable Benefits Manager to join our Human Resources team in San Jose, California. As we continue our hyper-growth trajectory as a leader in AI infrastructure connectivity, this role will be instrumental in designing, managing, and optimizing our global benefits programs that attract and retain world-class talent. This is a high-impact position that goes beyond day-to-day benefits administration. You'll serve as a strategic partner to HR leadership, analyzing market trends, ensuring compliance across multiple geographies, and driving initiatives that enhance the employee experience. The ideal candidate brings a global mindset, thrives in a fast-paced environment, and is passionate about building benefits programs that support our rapidly scaling workforce across the US, Canada, Asia, and EMEA. Key Responsibilities Benefits Strategy & Program Management - Develop and execute a comprehensive global benefits strategy aligned with Astera Labs' growth objectives and talent acquisition goals - Evaluate and

Principal Firmware QA Engineer Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Title : Lead Firmware QA Engineer , A stera Labs, Bengaluru, India. Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. Basic Qualifications : - Bachelor's degree in electrical engineering (EE) or Computer Science is required; a master's or PhD in EE is preferred with minimum 4 years of experience. Required Experience : - Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol. - Estimate work, identify dependencies and develop schedules. - Responsible for designing and executing functional, performance, interoperability and stress tests. - Work closely with Silicon team, architecture team, FW development team to understand the

Lead Firmware QA Engineer Bangalore, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Title : Lead Firmware QA Engineer , A stera Labs, Bengaluru, India. Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. Basic Qualifications : - Bachelor's degree in electrical engineering (EE) or Computer Science is required; a master's or PhD in EE is preferred with minimum 4 years of experience. Required Experience : - Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol. - Estimate work, identify dependencies and develop schedules. - Responsible for designing and executing functional, performance, interoperability and stress tests. - Work closely with Silicon team, architecture team, FW development team to understand the design

Senior Embedded Software Engineer - Ethernet Retimers San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs' Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications at the heart of AI infrastructure. As AI clusters scale to tens of thousands of GPUs connected by high-speed Ethernet fabrics, the firmware running on these connectivity devices is mission-critical - and so is the ability to debug it fast when something breaks. We're looking for a Firmware Engineer who can bridge our system validation team and firmware development organization. When something goes wrong in the lab or in the field, you won't be waiting on others to dig into the firmware. You'll be the person in the room who understands both sides - can pull up the code, identify the problem, and fix it. If you've worked at a networking company, know how Ethernet actually works from the MAC down through the PHY, have

Hardware Lab Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Astera Labs Inc. is seeking an experienced and self-driven Hardware Lab Engineer to join our dynamic team in developing world class connectivity products for AI infrastructure. Job Description This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight. Key Responsibilities - Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs. - Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces - Install and configure servers, including FW, BIOS, OS, and network - RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization - Manage logistics

Senior Lab Validation Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Senior Lab Validation Engineer , you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions. You will: - Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. Collaborate with design, validation, and system engineering teams as needed. - Modify device firmware to test out engineering theories leading to potential fixes or production screens. - Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems. - Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability. - Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports. - Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.