Principal Design Verification Engineer

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About this role

Principal Design Verification Engineer San Jose, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification-from planning and test development to debugging and coverage closure-contributing to the success of cutting-edge SoC designs. Key Responsibilities - Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. - Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. - Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. - Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification. - Work with RTL designers to troubleshoot and resolve design issues. - Drive verification strategy and methodology for

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