ASIC Design Verification Engineer | UVM | Exp 8+ Years

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Verification Engineer | UVM | Exp 8+ Years Bangalore, India Join our team as a Senior ASIC Design Verification Engineer and drive the development of industry-leading ASIC solutions for Cisco platforms. Collaborate with multidisciplinary teams, lead complex verification processes, and contribute to high-impact projects in a dynamic, innovative environment. Shape the future of digital infrastructure with your expertise in ASIC design and verification.

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.