Sr Analog Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Senior From the posting source

Schedule

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

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About this role

Sr Analog Engineer Seongnam-si, Gyeonggi-do, Korea, republic of Company Description: Job Description: This position is in CMSD Korea, which is part of Renesas' Analog & Connectivity organization. The CMSD R&D team develops and industrializes highly configurable mixed-signal products for a wide range of applications, including but not limited to consumer, communication, computing, data center, industrial, and automotive applications. CMSD team is the pioneer and dominant market leader of the highly successful GreenPAK family of products. This customer configurable product and platform enables customers to differentiate their products, reduces BOM cost and development cost and time. CMSD team is continuously expanding our product portfolio that includes high performance analog IP's, DC-DC, and FPGA. Understand the transistor- and system- level architecture. Ensure the performance of the high precision analog block to meet process, voltage, and temperature (PVT) variations. Contribute to the high-performance silicon-proven IP development. Collaborate with digital engineers on trimming and control for analog circuit. Guide to layout engineer to minimize the layout effects. Perform hands-on evaluation of IPs to use equipment like multimeter and oscilloscope. Collaborate with test engineering to ensure adequate test coverage. Analyze the ATE & CHZ data to validate product specification. Interface and Support with various teams in design view. Participate in root cause analysis of performance and functional issues. Modeling of analog and mixed-signal circuits for top-level testbench. Qualifications: 1. M.D. or Ph.D in EE semiconductor design by using CMOS 2. Strong knowledge in design and layout of analog and mixed-signal circuit design and architecture with

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